Product category:
Intellectual Property Cores
News Release from: Cambridge Consultants | Subject: CCLasic
Edited by the Electronicstalk Editorial
Team on 05 November 2002
Mixed-signal IP library includes
low-power radio
Cambridge Consultants (CCL) has released a novel silicon intellectual property (IP) library to the commercial SoC and ASIC markets.
Cambridge Consultants (CCL) has released a novel silicon intellectual property (IP) library to the commercial SoC and ASIC markets Developed and refined over more than 15 years, the new IP library focuses on mixed-signal building blocks including lean CMOS software-defined radio and processor cores
This article was originally published on Electronicstalk on 5 Nov 2002 at 8.00am (UK)
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The library can be accessed on the Cambridge Consultants website.
"Industry and commerce are only starting to scratch the surface of the potential of wireless connectivity", says Nick Horne of Cambridge Consultants.
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"There's a tidal wave of products waiting to exploit the technology, as soon as silicon costs reach a new threshold, which we believe is sub-two-dollars - and in some segments a dollar or less".
"Current mainstream RF standards don't offer a cost-effective option.
Proprietary RF system-on-chip implementations - optimised for the application - offer a viable route to success in the medium term.
This is a key focus of the new IP library, which we anticipate will catalyse a step-function advance in product capabilities", continues Horne.
Viewed as a whole, CCL's IP launch introduces a comprehensive family of interoperable components for mixed-signal control and communications applications - all of which have been field proven on design projects, many involving multi-million production quantities.
This addresses the single most important criteria in selecting IP following a component's fundamental performance: the availability of all functions required from one supplier.
Moreover, as many of the target applications for this emergent technology are in organisations with limited experience of embedded systems design, CCL is supporting the launch with comprehensive development services.
This extends to the turnkey design of entire products if required, thanks to CCL's multidisciplinary engineering resources.
The new mixed-signal IP library is called CCLasic.
It incorporates three main categories of silicon IP for ASIC and SoC applications: radio, processor and data convertor functions.
In total, there are over 20 building blocks.
Each comes with comprehensive documentation and support including test routines.
Analogue designs are provided as hard macros, for processes including 0.35 and 0.18 micron.
They are suitable for fabrication by commercial CMOS foundries, and can be ported on request to other geometries/processes.
Digital circuits come in the form of synthesisable, process-portable, Verilog RTL.
The circuits are ideal for applications in the unlicensed ISM (industrial, scientific, medical) frequency bands, and include radio subsystems - plus associated components such as band pass filtering and low noise amplifiers - A/D functions, lean RISC processor and DSP cores.
One of the particularly innovative architectures available through the library is software-defined radio.
CCL's radio IP provides great flexibility of application, and is designed for manufacture using pure-play CMOS.
Together, these attributes allow single chip solutions embracing control and communications functions to be fabricated very economically, using low-cost programmable digital circuitry.
The radio's programmability not only facilitates changes such as the use of different modulation and baseband processing schemes, but adds a flexibility that can dramatically shorten design cycles and avoid problems that might in other circumstances necessitate a costly re-spin of the chip.
Moreover, innovative design techniques have been employed to minimise the external components usually required, allowing complete radio-equipped systems to be built with a single chip and a few external passive components.
Complete SoC solutions with a silicon area of around 5 to 15mm2 are easily feasible using the IP, die sizes equating to prices of US $0.50 to $1.50 in volume production.
(This was Electronicstalk's Top Story on 2 November 2002).
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