IP library provides budget RISC processor blocks

Cambridge Consultants' new IP library provides proven interoperable components that allow mixed-signal, wireless enabled, SoC or ASIC solutions to be reliably and rapidly configured.

Cambridge Consultants' new IP library provides proven interoperable components that allow mixed-signal, wireless enabled, SoC or ASIC solutions to be reliably and rapidly configured.

Optimised for low cost and power consumption, the CCLasic library can deliver wireless connectivity today to new applications in cost-critical market segments including industrial instrumentation, toys and consumer goods.

Major IP blocks include a lean RISC processor core and software-defined radio.

The XAP2 microcontroller provides maths-oriented 16bit RISC processing capability optimised for SoC implementations.

Provided in the form of process-portable Verilog RTL, the processor will synthesise to around 12,000 gates.

This supports, for example, physical implementations in less than a square millimeter of silicon using a 0.35 micron CMOS process - equating to a typical cost of around US $0.10.

The design is optimised for very low power consumption, to suit battery powered applications.

Power reduction techniques include an extensive use of single cycle instructions, with an instruction set chosen for power efficiency, and a sleep mode that uses virtually zero power.

XAP2's quiescent current level is so low that 10 year battery lifetimes from a single button cell are achievable.

Comprehensive software development and debug tools are provided.

This architecture has been field proven in many applications including in the leading Bluetooth chip (CSR's BlueCore).

For versatility and economy, the CCLasic library offers software-defined radio building blocks, based on pure-play CMOS, that will operate in the unlicensed ISM (industrial, scientific, medical) frequency bands.

The modularity allows lean, application-specific, radios to be configured rapidly, with major performance characteristics such as the type of data modulation and the baseband signal processing determined using digital signal processing.

This approach allows changes to be made by means of firmware updates, throughout the development cycle, or even in the field - greatly reducing risk and potentially enhancing product lifecycles.

Using CCL's IP, complete software-defined radios including ROM, RAM and DSP elements may be implemented in silicon areas as small as 5mm2.

This equates to a typical volume fabrication cost of around US $0.50 using a 0.18-micron CMOS process.

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