Product category:
Intellectual Property Cores
News Release from: Cambridge Consultants | Subject: APE2
Edited by the Electronicstalk Editorial
Team on 11 February 2003
DSP core uses adaptive datapath to speed
to 1BOPS
A novel DSP core is claimed to establish a new price/performance benchmark for low-end SoC/ASIC applications.
Cambridge Consultants (CCL) has launched an innovative DSP core it reckons establishes a new price/performance benchmark for low-end SoC/ASIC applications Despite the core's very compact design - facilitating a 16bit implementation using as few as 7000 gates for example - a novel adaptive datapath architecture delivers startling computational throughput
This article was originally published on Electronicstalk on 7 Sep 2004 at 8.00am (UK)
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Advanced application-specific performance is achieved by allowing users to configure and customise the core's VLIW (very long instruction word) processing architecture, together with a highly parallel structure featuring dynamic datapath routing.
Processors may easily be configured to perform 10 parallel operations per cycle for instance, delivering 1BOPS throughput at a 100MHz clock rate - in a silicon area that equates to a volume manufacturing cost of a few cents Dubbed APE2, the new DSP core forms part of CCL's commercial silicon intellectual property library, CCLasic, and has already been field-proven on SoCs for software-defined radio as part of the consultancy's product design work.
"Most commercial DSP IP is targeted at high end applications and is difficult to cost-justify for cost-sensitive volume products, forcing companies to develop dedicated hardware", says Nick Horne of Cambridge Consultants.
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"APE2's blend of compactness and customisable performance opens up a new niche in the low-end embedded DSP space, allowing more OEMs to cut time to market and inject greater versatility into product designs".
The APE2 core features a parallel structure with processing modules such as single cycle MACs (multiply accumulators) and ALUs (arithmetic logic units) connected to a common data routing bus.
Users configure the DSP for the application by choosing the appropriate processing module functions and quantities from the library, and configuring the width of the databus, in increments as small as a bit at a time.
APE2's data routing bus supports further optimisation by allowing the output of any processing module to be made available at the input of any other, and by further letting the datapath connection or connections change from instruction to instruction.
This innovative feature allows designers to create optimised computational structures for each instruction or subroutine - and perform multiple operations in parallel - effectively providing dynamic hardware reconfiguration.
A DSP's arithmetic modules might be connected in a wide parallel structure to rapidly process audio data for example, and then reconfigured to handle smaller data widths such as sensor inputs, at a later stage in the algorithm.
The dual level of optimisation stemming from APE2's dynamic datapath routing and hardware configurability gives designers enormous latitude to implement powerful application-specific signal processing and control algorithms using tiny amounts of silicon real estate.
Moreover, the dynamic datapath routing gives OEMs enormous freedom throughout the design cycle to modify designs to accommodate changing requirements, and even to fix bugs - the biggest challenge facing SoC/ASIC projects.
"Although the resources on the core are limited compared with most commercial IP, the hardware configuration and algorithmic flexibility that may be achieved can deliver exceptional performance for some categories of applications", adds Nick Horne.
APE2's library of processing modules includes MAC, ALU, FFT, Cartesian-to-polar conversion, sequencing, I/O registers, and memory interfaces.
Custom processing modules may also be included.
A powerful tool suite is provided with licenses to embed APE2, supporting hardware selection, code generation for any hardware configuration, design optimisation including code compression, and graphical simulation.
The tools automatically generate Verilog source code including any decompression hardware.
The tools provide users with complete control and flexibility over their DSP design, but CCL will also produce custom designs for users on request.
Typical applications for APE2 include highly integrated software-defined radios, integrated sensor systems and audio processing, for markets such as consumer appliances, toys, and industrial instrumentation.
The CCLasic library includes proven IP blocks required to generate mixed signal ASIC/SoC designs for applications including software-defined radio building blocks and RISC processors.
The DSP is also suited to act as a coprocessor to speed system throughput, and CCL can provide a ready-to-use interface for its lean RISC core, XAP2.
The functional flexibility opened up by the configurability of the DSP hardware and the data routing bus gives product designers considerable latitude to exploit APE2 to reduce NRE costs for products requiring different capabilities for different markets.
One DSP core design could be programmed to support different wireless data modulation schemes for example.
And, with a degree of flexibility incorporated into the initial hardware configuration of the core, designers could easily use the DSP to add functionality to products over time - reaping enormous benefits in terms of time to market and NRE reduction.
Alternatively, a developer can use the optimisation facilities built into the tool suite to make APE2 designs as economic as possible, by identifying unused or seldom used resources such as datapaths, and eliminating these to make the design highly application specific.
APE2 project implementation licenses are available for single or multiple uses.
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