RTL debugger makes sense of third-party IP

A customisable tool helps designers of IP-based SoCs reduce the complexity of the debug process and makes it easier to understand and change register-transfer level code.

New from Concept Engineering, RTLvision Pro is a customisable tool to help designers of intellectual property (IP)-based SoCs reduce the complexity of the debug process and makes it easier to understand and change register-transfer level (RTL) code.

With the addition of RTLvision Pro to Concept Engineering's product line, the company now offers interactive visualisation and debugging tools for all major design levels: RTL, gate-level and transistor-level.

Integrated circuit, SoC and FPGA design and verification engineers who develop, integrate and debug RTL code and IP components are facing increasing productivity pressure as designs become more complex and challenging.

Designers often alleviate this pressure by using IP-based SoC design methods.

RTLvision Pro allows these designers to quickly understand, integrate and debug third-party or "inherited" IP.

"For RTL designers, code is what really counts", said Gerhard Angst, President and CEO of Concept Engineering.

"We have capitalised on our long experience in gate-level and transistor-level debugging to provide these designers with a very fast and innovative link between code and interactive graphic fragments".

RTLvision Pro helps engineers reach faster RTL code closure by enabling quick visualisation of critical design fragments and easy understanding of design behaviour and design miss behaviour.

With mixed-language support for System Verilog, Verilog and VHDL and ultra-fast HDL readers, RTLvision Pro can be used on today's most complex heterogeneous designs.

This easy-to-use, high-performance tool helps reduce the complexity of the debug process via its interactive logic cone navigation feature, which shows just the critical portion of the RTL design in the logic cone window while concurrently providing links to the original source code.

As a result, engineers can easily work on the important critical fragments of their RTL project without being disturbed by code and graphics not relevant for the job at hand.

RTLvision Pro also: automatically extracts and analyses clock trees and clock domains; supports detection and resolution of clock domain problems; allows incremental design compilation for very fast design update; and provides a TCL-based UserWare application programming interface (API) that allows highly flexible customisation, allowing the designer to extend the functionality of RTLvision Pro to meet the immediate needs of the project.

Free evaluation packages for RTLvision Pro are available from Concept's website.

Initial product demonstrations will be provided on Booth 720 at the Design Automation Conference (DAC) 2006 in San Francisco.

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