Interface sheds light on parasitic effects

Edited by the Electronicstalk editorial team Apr 16, 2007

DSPF interface will enable design engineers to better understand, manage, and fix parasitic structures within complex digital, mixed-signal and analogue ICs.

Concept Engineering has announced a new detailed standard parasitic format (DSPF) interface to the company's SpiceVision Pro and SGvision Pro products that will enable design engineers to better understand, manage, and fix parasitic structures within complex digital, mixed-signal and analogue ICs.

Using nanometre process technologies, IC designers are able to build systems comprising millions of transistors.

However, extremely compact devices and more complex interconnect structures require detailed modelling of parasitic effects and make it necessary to conduct transistor-level post-layout analysis and simulation in order to detect potential functional failures.

The layout of an integrated circuit (IC) contains an enormous number of parasitic devices resulting from the interconnections and components of the chip.

Such parasitic networks, often modelled as DSPF files, describe the parasitic resistance and capacitance of signal nets within an IC.

"The new DSPF capability was developed in response to customer requests to help them better understand and manage parasitic structures on their ICs", said Gerhard Angst, President and CEO of Concept Engineering.

"This new capability is based on our existing market-proven SpiceVision Pro environment, currently in use by more than 70 semiconductor companies and electronics manufacturers worldwide".

DSPF is widely supported by many electronic design automation (EDA) tool vendors.

With the new DSPF interface, design engineers using SpiceVision Pro and SGvision Pro will be able to easily read, explore, and analyse parasitic structures in order to better understand, and manage parasitic elements within their IC designs.

The interface generates and displays schematics of the parasitic networks, providing engineers with very detailed information about the structure and values of interconnections on their chips.

Cross probing from parasitic schematics to DSPF source code enables engineers to know the exact location of parasitic devices in the chip layout.

Concept Engineering's DSPF capability will be demonstrated for the first time on Stand R34 at the 2007 DATE (Design Automation and Test in Europe) Conference in Nice, France from 17th to 19th April.