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CebaTech
Address:
444 Route 35 South
Eastontown
NJ 07724
USA
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Listing of all 8 news releases from CebaTech:
Cores secure storage SoC designs
IP cores provides comprehensive standards-based lossless data compression for use in storage and data networking ASICs and FPGAs.
News from CebaTech (15 May 2007)
IP cores join online chip design community
CebaTech has joined the Chip Estimate Prime IP Partner programme.
News from CebaTech ( 8 May 2007)
Modular IP cores for FPGAs and ASICs
The CebaIP Platform is a modular approach to offering IP cores that allows design engineers to integrate functions quickly into AICs of FPGAs.
News from CebaTech (30 April 2007)
Compiler technology complements HyperTransport
CebaTech has joined the HyperTransport Technology Consortium.
News from CebaTech (18 January 2007)
Compiler generates RTL from untimed ANSI C
C-to-RTL compiler works efficiently on large, complex designs at a high level of abstraction and then automates the process of creating high-performance hardware solutions.
News from CebaTech ( 8 January 2007)
C-to-RTL compiler technology explained
CebaTech will participate in the Xilinx ESL for FPGA Training Forum on 6th November 2006 at the Hilton Hotel, San Jose, California.
News from CebaTech ( 6 November 2006)
Funds pave the way to commercial products
New funding will enable CebaTech to focus on productising ESL compiler technology and Internet Protocol cores developed using the ESL compiler.
News from CebaTech (24 July 2006)
Strategy centres on IP IP and ESL technology
CebaTech has unveiled its strategy to deliver high-value, high-performance Internet Protocol intellectual property and breakthrough ESL technology to companies developing ASIC and FPGA solutions.
News from CebaTech (18 July 2006)

