C-to-RTL compiler technology explained

Edited by the Electronicstalk editorial team Nov 6, 2006

CebaTech will participate in the Xilinx ESL for FPGA Training Forum on 6th November 2006 at the Hilton Hotel, San Jose, California.

CebaTech has joined the Xilinx Alliance Programme, a scheme designed to provide customers with total solutions, combining Xilinx programmable logic with key technologies from programme members, including IP cores, EDA, DSP and embedded development tools, design services, board-level products, integrated circuits and electronic components.

In addition, CebaTech will participate in the Xilinx ESL for FPGA Training Forum on 6th November 2006 at the Hilton Hotel, San Jose, California.

The event will provide an opportunity for the design community to gain an understanding of the usage and immediate benefits of electronic system level (ESL) tools and methodologies as they apply to field programmable gate array (FPGA) design.

At the training forum, CebaTech, also a member of the Xilinx ESL Initiative to accelerate adoption of system level design for FPGAs, will host four 90-minute sessions covering its C-to-RTL compiler technology.

System architects, hardware designers, and software engineers have the opportunity to attend one of these sessions to learn how untimed ANSI C code can be used to implement complex software algorithms in FPGA hardware.

The complete flow, from C source code to RTL code generation, RTL simulation, and Xilinx ISE-based FPGA synthesis, will be presented and demonstrated.