Celoxica offers a free go at FPGA design

Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.

Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.

With this evaluation version of the design suite engineers can build functional, accurate modules of designs without real hardware.

This powerful version of the design suite is available, free of charge from the Celoxica website.

System requirements and full details are posted on the site.

Marconi was one of the first companies to take advantage of the DK1 design suite.

It has recently signed a 10-seat licensing and partnership agreement with Celoxica.

"Electronics manufacturers are increasingly using FPGAs in the design process, supplementing the use of ASICs", said Jack Fryer, technology and strategy director at Marconi plc.

"We see the combination of DK1 with FPGA technology as a powerful design solution which we will exploit in forthcoming development projects.

Over the next few months Marconi will be undertaking major new projects using the DK1 design suite across all areas of the group including mobile telecommunications, access technologies, optical networking, and broadband communications including ATM and IP switching".

"DK1 brings significant benefits to the hardware design process.

Because it targets FPGAs with a high level C language without an intermediate HDL step we can as much as halve the length of a typical design cycle", said Stuart Barratt, senior technology consultant, Marconi plc.

Barratt continued, "The Handel-C programming language at the heart of DK1 shares ISO/ANSI C syntax so it is possible to make trade-offs between the hardware and software elements of a design at a much later stage in the process.

Handel-C is simple to manage and maintain so designs are easier to optimise.

We have found that in some cases this can lead to the generation of designs that are both faster and smaller than those developed in VHDL.

In a benchmark we conducted the DK1 design was completed in 24 days and the VHDL design in 43 days.

The DK1 design was written in fewer lines of code, clocked faster and was roughly 40 per cent smaller than the VHDL design".

Celoxica and Marconi struck a technology agreement in early 2000 to carry out a joint evaluation project, this allowed Marconi to use development versions of the DK1 design suite to conduct rapid hardware prototyping and embedded system reconfiguration.

Projects to date have included building and testing a concept IP phone.

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