Upgrade for programmable logic design suite

The latest version of Celoxica's DK1 Handel-C-to-hardware design suite includes new features for system-level hardware and software codesign.

The latest version of Celoxica's DK1 Handel-C-to-hardware design suite includes new features for system-level hardware and software codesign, cosimulation support for ARM and PowerPC embedded processors, improved synthesis, enhanced area and delay analysis, improved VHDL output, Verilog output, 100 times faster simulation, and support for Actel, Altera Excalibur and Xilinx Virtex II Pro devices.

The DK1.1 design suite supports the design, validation, iterative refinement and implementation of complex algorithms in hardware.

It includes built-in design entry, simulation, and synthesis - all driven by Handel-C.

Handel-C is based on ANSI-C extended with concepts for timing, concurrency, flexible-width variables and resource allocation to let software engineers and hardware designers quickly implement complex algorithms efficiently in hardware.

"With the launch of DK1.1 and introduction of PAL and DSM technologies, Xilinx's relationship with Celoxica is returning real value to its customers", said Rich Sevcik, senior vice president of the FPGA Products Group at Xilinx.

"The simplicity of Handel-C, PAL and DSM make it easier to achieve an optimal design partitioning between embedded processors and programmable gates.

These products will support Virtex-II Pro designers by providing a unique tool for fully exploiting the potential of Platform FPGAs.

We are pleased that Celoxica has chosen our Programmable World events in April as the venue for the first public unveiling of DK1.1".

"The embedding of high-performance programmable processors into high-density programmable logic opens up new possibilities for system design", said Paul Hollingworth, European marketing director at Altera.

"In order to fully benefit from the capabilities offered by products such as Altera's ARM-based Excalibur family, designers need a methodology which allows true codesign; enabling the rapid exploration of hardware/software tradeoffs.

Celoxica is in the forefront of this field, and we are pleased to continue our partnership with them and support the new capabilities built into DK1.1".

"FPGAs and PLDs are evolving into programmable systems that require knowledge of both hardware and software.

DK1.1 provides a codesign environment developed for both software engineers and hardware designers wanting to make informed decisions about the partitioning of systems incorporating algorithms such as data compression, encryption and protocol handling that are creating system performance bottlenecks", said Dennis Nye, senior vice president, worldwide sales and marketing at Celoxica Limited.

DK1.1 allows reprogrammable system-on-a-chip designers to make informed critical decisions about hardware/software partitioning.

With the new mixed-language facility users can call C/C++ functions from Handel-C descriptions and Handel-C functions from C/C++ programs.

Apart from allowing designers to explore different partitioning schemes using a "what-if" scenario, software functionality can now be converted to hardware iteratively providing designers with a greater level of certainty when implementing elements of a system model in hardware.

The mixed-language approach also allows hardware designers to use C/C++ test benches to verify Handel-C designs.

DK1.1 outputs readable, structured Verilog and VHDL with the hierarchy of the Handel-C source code preserved so that hardware designers can debug the Verilog or VHDL output using conventional simulation tools.

DK1.1 provides a path to traditional HDL tools for those customers wanting to target ASICs.

The HDL output can be generated for a range of synthesis and simulation tools.

This new feature allows the designer to specify a synthesis or simulation tool of choice, from which the compiler generates the appropriate HDL output with the necessary tool-dependent attributes.

Synthesis tools supported by DK1.1 include Exemplar Leonardo Spectrum, Synplicity Synplify and Synopsys FPGA Express.

For simulation, DK1.1 supports Model Technology ModelSim.

The EDIF output stage has been modified to shorten design time by producing more readable signal names to aid back reference from place and route tools to the original Handel-C source code.

DK1.1 users can now directly target a wider range of programmable devices with additional support for: Xilinx Virtex II Pro; Actel EX, 54SX, 54SX-A, RT54SX, RT54SX-S, ProASIC and ProASICPLUS; and the Altera Excalibur EPXA10.

The simulator has been improved with speeds, on average, faster by a factor of 100.

DK1.1 has improved synthesis results and enabled early timing and area analysis through a new technology mapper that maps functionality to look-up tables (LUTs) rather than gates.

By mapping to LUTs, DK1.1's timing analysis tool gives designers an estimation of time and area before place and route.

Cosimulation support is provided for the embedded processors shipped with Xilinx VII PRO (PowerPC), Altera's Excalibur XA10 (ARM) via ModelSim, Simulink.

Verilog cosimulation is supported via ModelSim, to complement the existing support for VHDL.

DK1.1 supports cosimulation at two levels of abstraction: functional accurate and cycle accurate.

Functionally accurate cosimulation is useful in the earlier stages of a project, during system modelling, where Handel-C modules will call functions in C/C++ and vice versa.

Cycle accurate cosimulation with processors (ARM and PowerPC), VHDL and Verilog is provided for more detailed simulation.

Cycle-accurate models of the processors are run in ModelSim, which is connected directly to the DK1.1 simulator so that the user can analyse bus interaction.

Multiple DK1.1 or ModelSim simulators can be run concurrently to simulate several parts of a design.

Supporting DK1.1 is Celoxica's Platform Abstraction layer (PAL) API and Data Stream Manager (DSM).

PAL and DSM borrow a successful model from the software world by leveraging libraries of predefined functionality to access processors and peripherals via common APIs.

PAL is an API for accessing peripherals that abstracts away the underlying devices and presents instead a simple and consistent interface for migrating Handel-C applications between hardware platforms.

By providing an OS type environment for Handel-C FPGA/PLD designs, the user saves time by focusing on adding value to the design rather than detailed hardware interfacing issues.

Developed in partnership with Wind River, DSM is an API for communicating between hardware and software that abstracts away underlying bus transport.

DSM allows simple integration between microprocessor applications and Handel-C programs.

The technology enables multithreaded communication between FPGAs/PLDs and CPUs while shielding the developer from hardware details to reduce development time.

Through DSM, FPGAs/PLDs can be quickly deployed as coprocessor accelerators to address CPU bottlenecks by configuring data-intensive software to parallel hardware in real time.

DK1.1 for Windows 98, 2000, NT and XP will be available worldwide from April 2002.

DK1.1 for Sun Solaris 2.6, 7, 8, and Red Hat Linux version 7.1 will be released in June 2002.

DK1.1 is available as a free upgrade to current DK1 users.

New licenses cost from $35,000.

PAL and DSM will be sold separately.

(This was Electronicstalk's Top Story on 26 March 2002).

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