Product category:
Design and Development Software
News Release from: Celoxica | Subject: DK1
Edited by the Electronicstalk Editorial
Team on 13 August 2002
M-Tec Wireless shaves months off
development
M-Tec Wireless used Celoxica's DK1 design suite in the development of a custom processor for its widebeam modules.
M-Tec Wireless used Celoxica's DK1 design suite in the development of a custom processor for its widebeam modules With DK1, M-Tec was able to re-implement a processor design in an FPGA using Celoxica's Handel-C hardware programming language that was 50% faster overall and 30% faster than in VHDL
This article was originally published on Electronicstalk on 6 Feb 2001 at 8.00am (UK)
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Celoxica has announced the DK1 design suite, software that enables a fundamentally new approach to the design of electronic hardware.
Celoxica offers a free go at FPGA design
Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.
Wind River Systems, Celoxica's global distribution partner, introduced M-Tec to the idea of implementing low-level algorithms such as MAC processing in FPGAs using DK1.
"At our first meeting with Celoxica the company demonstrated a Spartan II based design in which a complex 3D graphics model was being rotated while live video input was being texture-mapped to its surface.
You could not have designed such functionality into a 200,000 gate FPGA using VHDL.
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Celoxica has extended its DK1 design suite for the rapid design of reconfigurable hardware to support Xilinx Virtex II customers.
PII uses Celoxica DK1 to help pigs' data fly
PII has adopted Celoxica's DK1 design suite to improve design efficiency in the development of new hardware systems processing up to 6Mbyte/s of data for PII's fleet of "Intelligent Pigs".
Methodology cuts weeks off flow meter design
Celoxica has secured the sale of DK1 design suite licenses to Foxboro, a unit of Invensys Process Systems, to create FPGA-based Coriolis flow meters for process measurement applications.
I don't believe that C is a good language for hardware design because it lacks parallel expression.
But I could see that the parallel and timing extensions from Occam that Celoxica had applied to ANSI-C in developing the Handel-C hardware programming language were going to be especially valuable.
I visited Celoxica's headquarters.
While there, I re-implemented our existing VHDL solution using the DK1 suite in just one day.
I was hooked", said Jan Mennekens, chief technical officer at M-Tec Wireless.
M-Tec's widebeam broadband wireless LAN modules are configurable for HiperLAN/2, IEEE 802.11a++, wireless Ethernet and HiSWANa standards, achieving speeds of up to 54Mbit/s and higher.
The modules integrate transmitters and receivers together with protocol interfaces and a processing section that provides extra calculations such as error detection and correction, encryption/decryption and insertion of extra payload information.
Most of these operations are manageable by software on general processors, but market demand for higher performance and flexibility, smaller size, lower cost and power consumption led the company to look at integrating the key bottleneck functions directly in hardware.
"We wanted a new design in which high-level software sat above lower-level digital functions, and the OFDM modem layer at the base of the stack.
This led us quite naturally to a basic partitioning of the design.
Timing requirements are measured in milliseconds for the high-level functions, but we need to get into the 100ns region for lower level algorithms.
That led us straightaway to decide on dedicated hardware for the fastest functionality, and software running on a standard CPU for higher levels", said Mennekens.
M-Tec chose FPGAs as the hardware platform because production volumes could not justify the NREs associated with going to an ASIC.
FPGAs also provided additional benefits such as faster time to hardware implementation with the flexibility of not being forced down the route of one specific protocol.
"Before meeting Celoxica, we were using familiar VHDL tools to design a core for data movement.
An advantage of giving the FPGA a processor-like core is that top-level CPU software and MAC processing hardware can communicate readily via shared memory and a simple interrupt line.
There is no need for complex interfacing", explained Mennekens.
Mennekens continued: "Designing a new core was a difficult route to follow but we could not find a suitable DMA engine that could move data at rates in excess of 50Mbit/s with the intelligence of a processor, and processors within our target price range did not move data fast enough.
So we decided to design our own hybrid core with DMA performance and processor intelligence.
With several iterations and simulations this took us around six months to perfect in VHDL".
M-Tec Wireless bought a Celoxica-supported DK1 design suite license.
The resulting design was both smaller and faster than the original VHDL.
With around 400 lines the Handel-C code is 50% smaller than the VHDL code, even including the extensive commenting and documentation.
The Handel-C design also runs significantly faster, requiring around four clock cycles per instruction compared with VHDL's eight - and can be clocked at around 120MHz compared with 80MHz of the VHDL implementation.
"For the core, we couldn't have done better than Handel-C", concluded Mennekens.
"On the other hand, we felt that for interfacing to external hardware it would be better to use VHDL to design the actual interfaces and then Handel-C to hook them up".
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