Design software explained in Sophia

Celoxica is both exhibiting and presenting a paper at SAME 2002 (Sophia Antipolis Forum on Microelectronics) from 9th to 10th October.

Celoxica is both exhibiting and presenting a paper at SAME 2002 (Sophia Antipolis Forum on Microelectronics) from 9th to 10th October.

The company will be demonstrating the DK-1 design suite, a complete design flow from an algorithm written in C to an FPGA implementation.

The conference paper "Handel-C for co-processing and co-design of field programmable system on chip" will be given by Edouard Vincent at 16.20 on 10th October in the "Embedded software" session.

The paper uses as an example the re-engineering of a software system for Field Programmable System on Chip implementation.

The result was a 20x improvement in real-time performance, enhanced functionality and reduced number of components.

While the example is a radar processing system, the same advantages can be seen in a wide range of other applications.

DK1 Features and Benefits The DK1 design suite targets the design, validation, iterative refinement and implementation of complex algorithms in hardware.

It includes built-in design entry, simulation, and synthesis - all driven by Handel-C, a design-entry language based on ANSI C that combines parallelism with a central timing model.

Developers with knowledge of the C programming language find DK1's Handel-C language simple to use.

With its intuitive hardware-specific constructs, Handel-C lets software developers quickly code hardware designs.

DK1's integrated Handel-C-to-gate-level synthesis and optimisation eliminates the need for any interim HDL stage or the need to maintain any additional code stream.

The integrated Handel-C compiler lets developers generate optimised EDIF netlists appropriate for targeting FPGAs using FPGA manufacturers' tools.

In addition, DK1 can optionally generate VHDL and Verilog for traditional ASIC flows.

Back to top