Product category:
Design and Development Software
News Release from: Celoxica | Subject: DK2 Design Suite
Edited by the Electronicstalk Editorial
Team on 28 May 2003
C synthesis joins FPGA design flow
The latest version of Aldec Active-HDL now supports C synthesis through its interface with Celoxica's DK2 Design Suite.
The latest version of Aldec Active-HDL now supports C synthesis through its interface with Celoxica's DK2 Design Suite By adding support for Celoxica's C-based FPGA synthesis tool, system designers are now able to support VHDL, Verilog, C/C++, and Celoxica's Handel-C from a common, unified environment
This article was originally published on Electronicstalk on 6 Feb 2001 at 8.00am (UK)
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Celoxica has announced the DK1 design suite, software that enables a fundamentally new approach to the design of electronic hardware.
Celoxica offers a free go at FPGA design
Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.
"HDL designers have been benefiting from Active-HDL's integration and fast simulation performance for years.
Through our collaboration with Celoxica, that same industry-leading performance can now also benefit C and C++ designers", stated Megan Moran, Product Marketing Manager for Active-HDL.
"By ensuring compatibility with Celoxica's DK2 Design Suite, the leading C synthesis tool on the market, Aldec is continuing to provide the most advanced FPGA design and verification software to an even greater range of hardware engineers".
Further reading
Design suite extended to latest FPGAs
Celoxica has extended its DK1 design suite for the rapid design of reconfigurable hardware to support Xilinx Virtex II customers.
Board helps with small to medium FPGA prototyping
New from Celoxica, the RC100 stand-alone development board provides a rapid prototyping platform for small- to medium-sized FPGA designs.
PAL simplifies FPGA application interfacing
Celoxica has announced its platform abstraction layer (PAL) strategy for FPGA and system independent reconfigurable designs.
Active-HDL 6.1 simultaneously supports HDL as well as C/C++ source code all the way through to implementation.
Designers can use Active-HDL's leading design entry environment to develop code, and then invoke both HDL and C synthesis tools directly from its design flow manager.
Active-HDL's design flow manager provides a flowchart and direct interface access to Celoxica's Handel-C-to-hardware DK Design Suite.
Designers can access and control DK2 Design Suite directly from Active-HDL and translate their C and Handel-C-based designs to VHDL, Verilog or EDIF, which can then be integrated into Active-HDL's common kernel simulation environment.
With the evolution of digital designs, system designers are constantly looking for more efficient means and methods to develop source code and expedite time-to-market.
Common support of the various source languages is critical so that designers do not have to allocate development time on unifying source code to a single language.
Celoxica's DK2 Design Suite makes designers more efficient by raising the level of design abstraction through the use of higher-level languages such as C, C++, SystemC or Handel-C.
The Celoxica design methodology, called software-compiled system design, improves productivity by generating device-optimised FPGA hardware directly to EDIF or human-readable RTL from C-based descriptions.
This methodology also improves quality of design by allowing designers to find more optimal partitions between hardware and software.
Active-HDL's new interface with Celoxica offers designers the most complete FPGA design solution on the market.
In the Active-HDL environment, C users can specify the output format of their C-synthesis (VHDL, Verilog or EDIF), set the top-level unit for C-synthesis as well as set the family, device and speed grade of the target silicon.
All of the C-synthesis results from Celoxica are back-annotated in the Active-HDL environment so that users do not have to switch between applications, for ease and efficiency in design.
All synthesis results can be viewed in Active-HDL's synthesis log and modified accordingly in order to develop the most efficient end-device available.
"Celoxica is pleased that Aldec chose the DK Design Suite to extend the benefits of higher-level language design to their users", stated Graham McKenzie, Product Marketing Manager for Celoxica.
"This new interface creates a complete FPGA environment joining the C-based productivity of Software-Compiled System Design with existing HDL methodology.
This combination will give designers the fastest and most comprehensive route from source code to FPGA implementation".
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