FPGA design environment gives best of both worlds

Active-HDL+C is an integrated FPGA design environment that combines Aldec's Active-HDL design entry and mixed-HDL simulation technology with Celoxica's DK engine for C-synthesis and cosimulation.

Active-HDL+C is an integrated FPGA design environment that combines Aldec's Active-HDL design entry and mixed-HDL simulation technology with Celoxica's DK engine for C-synthesis and cosimulation.

Extending Aldec's recently announced support for Celoxica's C-synthesis tool, the combined Active-HDL+C package offers FPGA designers the productivity gains of mixing HDL with Handel-C from one integrated environment.

The designer is not required to learn multiple design entry and verification tools; therefore, design creation, project management, documentation, HDL simulation, cosimulation (HDL and C), C-synthesis as well as interfaces to third party FPGA place and route tools are controlled within a single flow.

"This partnership with Celoxica is a natural extension of our goal to provide increased productivity to FPGA designers", said David Rinehart, Director of Marketing at Aldec.

"Combining the powerful elements of Celoxica's Handel-C language with Active-HDL will allow users to implement functional specifications at the algorithmic level and then synthesise directly to the FPGA".

"The size and complexity of today's FPGAs demand the higher-levels of abstraction of C-based design", said Jeff Jussel, Vice President of Marketing at Celoxica.

"This joint package ensures that designers can take advantage of those higher-levels of abstraction in a way that fits seamlessly with their existing RTL IP and design flows".

Active-HDL+C provides a comprehensive FPGA design environment that supports both traditional RTL as well as emerging C-based flows.

The package provides block-based design entry for VHDL, Verilog and Handel-C, and then performs cosimulation of these blocks on a single screen from within Aldec's mixed-language environment.

By integrating Celoxica's C-synthesis and cosimulation technology with Active-HDL, users can simulate C with HDL and compile software algorithms directly into device-optimised FPGA hardware, giving FPGA designers access to the latest devices from Actel, Altera and Xilinx.

The package completes the design flow with timing simulation (EDIF Netlist or HDL netlist with SDF).

The Active-HDL+C package is now available through both Aldec and Celoxica sales channels worldwide.

Introductory pricing will be available through the fourth quarter of this year for the USA and UK.

Pricing begins at $35,000 for a single-seat perpetual licence of the complete Active-HDL (PE) dual-language (mixed VHDL, Verilog and EDIF) and Celoxica DK (C-synthesis and cosimulation) FPGA design environment.

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