ESL design environment covers more devices

Version 3.1 of the DK Design Suite provides high-level system codesign, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and programmable SoC devices.

Version 3.1 of the DK Design Suite provides high-level system codesign, verification and C-based synthesis for complex algorithm implementation to high-density FPGA and programmable SoC devices.

The new release extends the functionality, integration and silicon coverage of Celoxica's leading ESL design environment and improves the quality of results and designer productivity for generating production grade FPGA designs and rapid ASIC and SoC prototypes.

DK3.1 also includes performance upgrades to the Nexus-PDK coverification environment and new device support in the integrated Platform Developers Kit (PDK) board and processor support packages.

DK3.1 improves support for the implementation path from prototype to SoC through advanced high-level synthesis featuring IEEE compliant VHDL and Verilog output, automatically generated from complex C algorithms.

The resulting RTL code is compatible with common ASIC design flows.

VHDL output conforms to the IEEE1076.6-1999 standard for VHDL RTL synthesis and uses the numeric_std standard synthesis package.

Verilog output conforms to the IEEE1364-2001 standard and supports signed arithmetics and other additions to the language.

The DK3.1 tool extends silicon coverage for direct C-language synthesis of complex algorithms to optimised EDIF netlists.

The version includes device support for Cyclone II and Stratix II from Altera Corp and the Virtex-4 family from Xilinx.

Additional features in DK3.1 include new optimisation capabilities and upgraded design and build status reports to provide users more comprehensive information access.

"Advanced FPGA design projects are increasingly defined by the need to quickly implement a complex system algorithm into the device architectures", said Jeff Jussel, Vice President of Marketing for Celoxica.

"FPGA design flows need to keep pace by delivering the system-level capabilities designers require".

"In DK3.1 we've raised the bar yet again in terms of features, functionality and maturity".

"Through codesign, system verification and C-based synthesis, DK3.1 users are able to harness the power and potential of the next generation FPGA and programmable SoC devices".

Version 3.1 of Celoxica's DK Design Suite is available immediately with tight integration to FPGA vendor software such as Altera's Quartus II v4.1 and ISE 6.3i from Xilinx.

Delivered with DK3.1, Celoxica's upgraded PDK packages support Nios, Nios II and MicroBlaze soft cores and all popular FPGA bus specifications including Avalon, FSL, OPB and PLB.

Also available, Celoxica's popular COTS boards integrate to DK3.1 to enable rapid implementation of SoC prototypes.

A new set of parameterised IP including an FFT library and a Cordic library is also available with the DK3.1 version.

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