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Product category: Design and Development Software
News Release from: Celoxica
Edited by the Electronicstalk Editorial Team on 24 January 2005

Programme formalises tool
interoperability

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Celoxica has formalised the interoperability between its Agility Compiler and DK Design Suite and the Design Compiler synthesis solution from Synopsys.

Celoxica has formalised the interoperability between its Agility Compiler and DK Design Suite and the Design Compiler synthesis solution from Synopsys Celoxica's design tools for system level codesign and the rapid development of custom intellectual property cores from C-algorithms, enable designers to retain their single source C files through design exploration, verification and implementation

Celoxica's ESL approach provides the capability for the automatic generation and synthesis of IEEE compliant RT level VHDL, Verilog and FPGA netlists from ANSI-C or SystemC algorithmic descriptions.

"Celoxica's tools have become a distinctive part of the ASIC/ SoC design flow, now that it connects to the leading hardware implementation flow", said Jeff Jussel, Vice President of Marketing for Celoxica.

"Linking the Celoxica ESL tools to Synopsys' Design Compiler tools is an important step in realising the full potential of ESL design".

The development and verification of tool interoperability is being managed through the Synopsys in-Sync programme.

The initial focus is the optimisation of RTL generated from Celoxica's tools for Design Compiler tools.

"For years Synopsys has initiated programmes of its own and worked with standards bodies and industry organisations to advance tool interoperability throughout the electronic design automation industry", said Karen Bartleson, Director of Interoperability at Synopsys "Through the in-Sync interoperability programme, Synopsys enables EDA vendors to identify and implement interoperable design flows that maximise the productivity of our mutual customers".

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