Product category:
Design and Development Software
News Release from: Celoxica | Subject: Agility Compiler for SystemC
Edited by the Electronicstalk Editorial
Team on 15 February 2005
Compiler enables working silicon from
SystemC
Agility Compiler for SystemC includes an array of advanced system design capabilities for the synthesis of SystemC models to hardware.
Celoxica has begun shipping Agility Compiler for SystemC to customers The v1.0 tool includes an array of advanced system design capabilities for the synthesis of SystemC models to hardware
This article was originally published on Electronicstalk on 20 Jun 2005 at 8.00am (UK)
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The new Agility Compiler for SystemC synthesis can generate RTL descriptions from transaction level models for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for PLDs.
The tool produces IEEE compliant RTL descriptions as input to popular ASIC/SoC synthesis flows, and generates gate-level EDIF netlists for high-density programmable logic devices.
With Agility Compiler, designers can produce working silicon from SystemC models much earlier in the design flow, accelerating system verification and SoC prototyping.
The direct path from SystemC to hardware closes a critical gap in the ESL design flow for successful SoC design from system-level models.
Further reading
FPGAs updated over the web
Celoxica has announced the DK1 design suite, software that enables a fundamentally new approach to the design of electronic hardware.
Celoxica offers a free go at FPGA design
Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.
Agility Compiler synthesises a complete hardware system with no artificial limitations on design hierarchy, structure, timing or interfaces.
Agility Compiler advanced synthesis technology supports multi-million gate designs, multiple blocks and multiple clock domains, easily beating the results of entry-level behavioural synthesis tools that restrict designers to small, single block, single clock domain designs.
In addition, Agility Compiler synthesis extracts accurate timing and physical design metrics to support fast cycle accurate simulation and test bench generation for system verification.
By allowing SystemC transaction level models (TLMs) to be automatically synthesised to RTL descriptions or FPGA netlists, system models are realised in FPGA based SoC prototypes much earlier in the design flow.
"Agility Complier drastically reduces the risk inherent in complex SoC design and enables designs to be turned around to meet a much shorter market window", said Jeff Jussel, Vice President of Marketing for Celoxica.
"The ability to synthesise from transaction level models tightens the link between the algorithm specifications, the system verification software, and the end hardware".
Agility Compiler's synthesis is driven from pure, standard compliant SystemC descriptions.
By avoiding the use of proprietary descriptions or linked constraints, the synthesisable SystemC code remains standard compliant and portable for model and IP reuse.
Agility Compiler is fully compliant with the OSCI standard SystemC synthesisable subset.
The Agility Compiler gate-level synthesis supports very high-density FPGA devices, such as Altera's Stratix II and the Virtex 4 family from Xilinx with advanced synthesis features such as retiming, fine-grained logic sharing, dead-code elimination, rewriting and automatic tree balancing.
This direct synthesis support enhances Agility Compiler's applicability to SoC prototyping, accelerated verification and rapid system implementation.
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