Atmel processors to gain ESL design support

Atmel Corp and Celoxica are working to extend electronic system level (ESL) design to a family of dynamically reconfigurable processors currently under development at Atmel.

Atmel Corp and Celoxica are working to extend electronic system level (ESL) design to a family of dynamically reconfigurable processors currently under development at Atmel.

These new backend tools are being developed for a new generation of processors based on Atmel's FPSLIC technology that is planned for introduction later this year.

Tools from Celoxica's ESL portfolio, the DK Design Suite and Agility Compiler will synthesise hardware accelerators from highly complex algorithms described in C or SystemC.

Celoxica will also provide its HW/SW codesign technology and board-level integration technology to offer Atmel customers a seamless implementation flow.

The tools are new to the industry because they allow for dynamic reconfiguration.

"On-demand, on-the-fly software and hardware programmability is becoming increasingly integrated and pervasive in modern systems development", said Guy Lafayette, Marketing Manager at Atmel.

"It is critical that we empower existing and new customers to efficiently harness this potential".

"By using design tools from Celoxica we can easily migrate to ESL and enable our customers to better explore the design space, evaluate partitioning tradeoffs and efficiently map complex designs onto a device".

More than 4 years of research undertaken at the Academy of Sciences of the Czech Republic has led to this co-operative development.

Researchers from the Academy's Institute of Information Theory and Automation (UTIA) collaborated with both Atmel and Celoxica to define and prove the flow from algorithm to implementation.

"By utilising using C-based design and synthesis from Celoxica we have demonstrated ease of design and lower cost of design coupled with production grade implementation", said Jiri Kadlec, Head of the Department of Signal Processing at UTIA.

"We have also demonstrated increased functional density of user designs and decreased power consumption by taking advantage of dynamic reconfiguration".

"We're delighted to be working with Atmel and UTIA in this important area of research, design and development", said Jeff Jussel, Vice President of Marketing for Celoxica.

"ESL design coupled with high-level synthesis delivers the productivity and efficiency gains that designers and modern reconfigurable architectures demand".

"By working with Atmel, we will extend design support to include not only high speed, high quality custom HW/SW implementations but also precompiled IP that further reduces the burden of complex design and verification".

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