ESL design speeds coprocessor from C to hardware

Celoxica has helped the Japan Advanced Institute of Science and Technology to develop a high speed digital watermarking detection system with real-time operation across the Internet.

Celoxica has helped the Japan Advanced Institute of Science and Technology (JAIST) to develop a high speed digital watermarking detection system with real-time operation across the Internet.

The joint research project used ESL design and C-based synthesis to accelerate watermarking algorithms in a hardware coprocessor.

The project resulted in a low-power solution that runs detection scanning 148 times faster than software only configurations.

The complex algorithm design was implemented using Celoxica's DK Design Suite of ESL tools and RC Series hardware platforms.

Digital watermarking is increasingly being used in response to the escalating misuse, and illegal copying and distribution of multimedia content.

Digital watermarks embed hidden data into digital content or media.

These watermarks contain copyright information identifying the origins, ownership and authenticity of the content.

The research project at JAIST developed an accelerated watermarking solution for audio content.

The project increased detection efficiency and implemented multiple watermarks in parallel using hardware coprocessing.

"Digital watermark detection by software alone is too slow and power hungry, and it cannot catch illegal audio files that are exchanged over the Internet", said Yasushi Inoguchi, Associate Professor at the Centre for Information Science at JAIST.

"Using C-based design and synthesis technology we were able to easily capture the complex watermarking algorithms and accelerate the watermark detection scheme in a co-processor, exploiting the power and performance benefits of programmable hardware".

Supported by Celoxica and Japan's Science and Technology Agency (JST), JAIST researchers used Celoxica's DK Design Suite to design the watermarking algorithms and implement them from C to hardware.

A Celoxica RC Series development board was selected as the hardware platform.

Tests using a benchmark for detection of 50 watermarks show that the JAIST solution achieved detection times of 500ms (326.4Mbit/s) running hardware coprocessing at 30MHz.

This compared with detection times of 74,351ms (2.2Mbit/s) for a Pentium 4 microprocessor running at 2.8GHz in a software only implementation.

"The level of performance improvement that was achieved makes it possible to perform real-time watermarking detection of content exchanged over a network", said Colin Mason, VP Asia Pacific, General Manager of Celoxica Japan.

"It provides yet another example of how designers are increasingly using our DK Design Suite and RC algorithm accelerators to speed-up systems and IP in different processing architectures, particularly where the mismatch between power and performance is becoming a critical design problem".

More information about this project has been published trough the IEICE Computer society.

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