Suite delivers full software to silicon flow

The fourth generation of the DK Design Suite is claimed to reset the bar for C-synthesis performance and deeply embeds the technology in standard SoC design flows.

The fourth generation of the DK Design Suite from Celoxica resets the bar for C-synthesis performance and deeply embeds the technology in standard SoC design flows.

Advanced memory utilisation increases design capacity and speeds synthesis execution, synthesis optimisation improves quality of results, and enhancements ease the software-to-silicon process and link ESL to physical SoC design.

Celoxica, the leading provider of C-based electronic system level (ESL) design and synthesis solutions with more than 350 commercial installations worldwide, delivers a complete design flow from ESL, to FPGA prototype, to SoC implementation.

DK4 introduces new VHDL and Verilog output optimisations for interfacing with Design Compiler from Synopsys.

In addition to RTL input for the SoC flow, DK4 also supports automatic scripting for SoC test bench generation.

This interface bridges the gap between ESL and latest SoC physical design and verification flows.

The advanced memory utilisation technology in DK4 supports designer productivity with synthesis of larger and more complex designs 30-50% faster over previous versions.

This speed enhancement allows DK4 to produce FPGA implementations directly from large software models.

Not limited to small single-block, single-clock modules like competing tools, DK4 can synthesise complete systems including complex algorithms, system interfaces and multiple clock domains.

Celoxica's unique C-synthesis tools automatically generate optimised EDIF FPGA netlists from high-level descriptions, turning software into silicon.

With the release of DK4, Celoxica strengthens this capability to deliver even better design quality of results (QoR) through the addition of improved technology mapping.

DK4 helps designers to better leverage the embedded ALU features and DSP blocks available in very high density FPGAs such as Stratix II and Virtex 4.

The silicon coverage in DK4 has also been extended to include the latest Xilinx devices; the high density Spartan 3E and the lower power Spartan 3L.

Algorithm designers can target all popular FPGA devices using a new GUI that offers a more intuitive and easy-to-use software-to-silicon flow.

Finally, Celoxica has extended DK Design Suite availability to users of the Linux OS.

"The DK4 release sets the benchmark for integrated ESL design productivity from system definition through implementation", said Jeff Jussel, Vice President of Marketing for Celoxica.

"We have significantly extended our position as the leading provider of C-based ESL design and synthesis for algorithm acceleration on FPGA, and bridged the gap between ESL and physical SoC design by optimising the connection from C to RTL to Design Compiler".

Version 4 of the Celoxica DK Design Suite is available for delivery in July in various package options ranging in list price from $10,000 to $80,000.

The DK Design Suite is available on Windows OS and, for the increasing number of designers choosing Linux as their OS of choice, DK4 now provides Linux support.

Back to top