System-level design speeds network cards to market

System-level design technologies are being used to support rapid development of advanced Internet protocol services such as IPv6 and multiprotocol label switching.

System-level design technologies are being used to support rapid development of advanced Internet protocol services such as IPv6 and multiprotocol label switching (MPLS).

The Cesnet research team in the Czech Republic is using Celoxica's DK Design Suite to develop firmware used in programmable hardware accelerators based on off-the-shelf programmable logic devices and implement the very complex protocols needed for IPv6 enabled applications.

Celoxica's platform abstraction layer API will be used to allow application reuse across different programmable hardware platforms without additional development.

The intellectual property created will be made available to other IPv6 development teams though open-source licensing.

IPv6 is intended to solve the address limitations of IPv4, with too few IP addresses available for the future demand of device connectivity that now includes mobile phones, computing devices and mobile networks.

Currently IPv4 supports only 4.2 billion addresses, which is inadequate for giving one address to every person, much less support the burgeoning market for fixed and wireless connected devices.

IPv6 addresses this problem by supporting 340 undecillion (10e36) addresses and gives the opportunity for high performance value added applications such as hardware accelerated virus scanning, spam filtering, content blocking and real-time video and HDTV over IP.

"Cesnet is one of the world leaders in IPv6 network deployments and we have been intensively working on the development of specialised programmable network PCI cards to accelerate IPv6 network traffic monitoring and packet routing", said Jiri Novotny, Leader of Cesnet Activity Programmable Hardware and system architect of Liberouter.

"By using C-based design to create firmware for our network accelerators, not only can we quickly implement the complex algorithms and models that are needed, but the IT professionals and end users who are familiar with C-based design can customise and tune the network devices themselves".

Called Combo, the family of wire speed IPv6 network accelerator platforms developed by Cesnet uses TI embedded processors and Spartan 3, Virtex II, Virtex II Pro and Virtex 4FX FPGA devices from Xilinx, with either PCI or PCI Express interconnect.

Programmed using Celoxica's DK Design Suite the Combo family gives developers the possibility to work with "open-hardware" and use it in the same way as open-source software.

Celoxica's platform abstraction layer (PAL) open-API means that the same developers can create IPv6 enabled applications and IP to a single set of interfaces and independent of board level detail.

"IPv6 provides the plug and play convergence layer needed between applications and the Internet and its deployment is critical to realising the promise of smart, connected devices in the home, work place and on the move", Jeff Jussel, Vice President of Worldwide Marketing for Celoxica.

"Our design solutions mean we can not only accelerate the performance of IPv6 enabled applications, but deliver them to the end user faster and support wider development though open source provision".

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