Product category:
Design and Development Software
News Release from: Celoxica | Subject: Agility Compiler
Edited by the Electronicstalk Editorial
Team on 17 January 2006
Compiler supports latest SystemC
standard
The new Agility Compiler for SystemC synthesis can generate RTL descriptions from transaction level models for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for PLDs.
Celoxica has announced the latest release of its Agility Compiler for SystemC synthesis supporting SystemC prototyping and verification The new release can generate RTL descriptions from transaction level models (TLM) for popular ASIC/SoC synthesis flows and gate-level EDIF netlists for programmable logic devices
This article was originally published on Electronicstalk on 9 Jun 2004 at 8.00am (UK)
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Compiler automates SystemC synthesis
The Agility compiler synthesises SystemC directly to high-density FPGA and programmable SoC logic and generates RTL VHDL and Verilog for SoC design.
Tools to support latest-generation FPGAs
Celoxica will support the newly introduced Virtex-4 FPGAs through the latest release of its suite of system design and synthesis tools.
SystemC 2.1, now known as IEEE P1666, provides a definitive description and a precise and complete specification of the SystemC language.
Implementations can now be confidently developed with reference to the SystemC standard with a common framework for collaboration.
As part of Celoxica's programme to improve integration of SystemC simulation and verification with synthesis, designers can now build simulations directly from the Agility Compiler GUI.
From the same source code files designers can verify their SystemC designs against the OSCI reference model in a single environment.
"Fundamental to the adoption of SystemC by our customers is standards compliance, ease of use and superior QoR targeting custom hardware and high density programmable logic", said Jeff Jussel, Vice-President of Worldwide Marketing for Celoxica.
"With the latest release of Agility we have demonstrated our commitment and currency with SystemC and strengthened its capabilities for prototyping, verification and production".
Improved code management and ease of use is supported through RAM inferencing and enhanced SystemC datatypes that also allow for better quality of results from less code.
Comprehensive feedback is provided to the developer though enhanced design reporting and synthesis analysis.
Agility's control and dataflow graph (CDFG) viewer allows the designer to accurately view, analyse and understand high-level designs, linking source code through to synthesis results and interactively browsing a graphical representation of the design.
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