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Design and Development Software
News Release from: Celoxica | Subject: Floating-point arithmetic toolkit
Edited by the Electronicstalk Editorial
Team on 21 July 2006
Floating-point arithmetic toolkit
New toolkit for floating-point arithmetic implementation in high-density programmable logic.
Celoxica has announced availability of a toolkit for Floating-Point arithmetic implementation in high-density programmable logic The IEEE 754 compliant libraries support single, double and custom precision Floating-Point
This article was originally published on Electronicstalk on 6 Feb 2001 at 8.00am (UK)
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Celoxica has announced the DK1 design suite, software that enables a fundamentally new approach to the design of electronic hardware.
Celoxica offers a free go at FPGA design
Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.
They are fully parameterizable for area, latency and performance optimisation across all leading programmable logic architectures and can be tuned to specific application requirements delivering industry-leading performance and unrivalled flexibility.
Developed in conjunction with the Institute of Information Theory and Automation (UTIA) in the Czech Republic, the underlying IP behind the Floating-Point ToolKit represents the first milestone between Celoxica and UTIA since the two organisations signed a multi-year research agreement.
The Floating Point ToolKit is being deployed into high-performance computing (HPC) application areas such as the automated trading of equities and related financial derivatives, oil and gas exploration and embedded applications including audio and video DSP filtering.
Further reading
Design suite extended to latest FPGAs
Celoxica has extended its DK1 design suite for the rapid design of reconfigurable hardware to support Xilinx Virtex II customers.
Board helps with small to medium FPGA prototyping
New from Celoxica, the RC100 stand-alone development board provides a rapid prototyping platform for small- to medium-sized FPGA designs.
PAL simplifies FPGA application interfacing
Celoxica has announced its platform abstraction layer (PAL) strategy for FPGA and system independent reconfigurable designs.
Parallel designs using the Floating-Point core modules can deliver up to 50 Giga Floating-Point Operations per Second (GFLOPS) and support the processing requirements in real-time imaging and signal processing applications, and compute-intensive routines typically used in clustered server and supercomputer architectures.
By exploiting the inherent parallelism of FPGA hardware exceptionally high Floating-Point arithmetic can be achieved with significant performance-per-watt energy savings.
The combination of the Floating-Point ToolKit with programmable logic means the number of instances of the Floating-Point operator is user configurable and scalable.
The Floating-Point ToolKit supports pipelined add, subtract, multiply, divide and square-root operations, and conversions to and from 32bit fixed point.
The add module has a five stage pipeline for all precisions and the multiply module is provided with user configurable pipelines to support the embedded multiplier and DSP blocks in modern FPGA devices.
18m12, 24m16, 32m24, 40m32, 64m53 precisions are supported as is IEEE754 rounding to the nearest and even.
The custom precisions provided in the ToolKit are optimised for designers who want to take maximum advantage of embedded FPGA resources such as DSP blocks and make optimum use of existing gate counts.
For simulation and verification the ToolKit supports processor-in-the-loop and hardware-in-the-loop simulation.
Bit-exact Simulink blocks for all arithmetic operations supported by the library (precisions 18m12, 24m16, 32m24, 40m32 and 64m53) are included and test vectors can be created in Simulink models and debugged in Celoxica's DK Design Suite.
Breakpoints help debug the implementation at the register level and DK's simulator reads data generated in the Simulink model and returns data back for verification of the bit exact results.
Implementation to the FPGA is supported with API layers that allow application reuse across different programmable platforms without additional development or recoding.
"This important addition to our IP portfolio addresses customer need in both the DSP and HPC space for a very high performance, fully parameterizable and platform independent floating point capability," said Chris Sullivan, director of strategic marketing for Celoxica.
"We can readily tune and re-tune the libraries to meet changing architectures and specifications, and the current implementation not only provides industry beating performance and flexibility, but the libraries themselves demonstrate the extreme circuit optimisation that can be achieved using the DK Design Suite".
The ToolKit is available from Celoxica in a variety of different configurations.
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