Product category:
Design and Development Software
News Release from: Celoxica | Subject: C++ coding support
Edited by the Electronicstalk Editorial
Team on 28 July 2006
Improved C++ Support In SystemC
Synthesis Tool
Celoxica has enhanced C++ coding support in its Agility Compiler high level design tool
Celoxica has enhanced C++ coding support in its Agility Compiler high level design tool, raising the level of design abstraction above SystemC for designers who need to boost productivity and for programmers less familiar with hardware design By using the C++ coding style developers can more easily exploit the productivity gains and simulation benefits of C level design without compromising area or timing optimisation
This article was originally published on Electronicstalk on 6 Feb 2001 at 8.00am (UK)
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Celoxica DK1 Eval is a free evaluation version of the Celoxica DK1 design suite that is restricted to compilations for simulation only, with no EDIF or VHDL output capability.
The Agility Compiler addresses the middle ground between the unfulfilled promise of push-button design and the register transfer level (RTL).
Agility gives support for C++ classes, templates and inheritance that provide powerful abstractions to shield low level detail from the core algorithm.
Communication between objects can be done using C++ member function calls or FIFO's, and the need to use internal SystemC ports and port mapping for object hierarchy has been removed.
To retain the use of standard C datatypes, data width reduction automatically trims variable widths.
Agility's support for thread processes means better ease-of-use for programmers and architects familiar with modern processors and avoids reliance upon low-level sc_methods.
"Customers demand a quality-of-results performance directly linked to a level of design abstraction that delivers measurable productivity gains, but with the necessary accuracy and control," said Jeff Jussel vice president of marketing and general manager of the Americas for Celoxica.
"Using Agility you can dive into the low level implementation detail, but it isn't mandatory".
"A simple C++ function call can be used to turn a C array into a RAM, or you can instantiate RAM blocks by hand and manually implement a low level RAM driver".
The Agility Compiler is a part of Celoxica's family of electronic system level (ESL) design solutions that address the issues of time-to-market, design complexity and high-performance computing.
Agility automatically generates RTL descriptions from high-level C/ C++/ SystemC source for popular ASIC/ SoC synthesis flows and gate-level EDIF netlists for high density programmable logic devices.
"Our roadmap for Agility lays out the path to untimed synthesis, but the skill of the designer remains the critical component in a design flow and we've built Agility around them," added Jussel.
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