FPGA coprocessor speeds HyperTransport design

Complete off-the-shelf hardware and software compiler design bundle for high-performance computing uses industry standard HyperTransport slots.

Celoxica, a member of the HyperTransport Technology Consortium, has announced availability of the first complete off-the-shelf hardware and software compiler design bundle for high-performance computing (HPC) using industry standard HyperTransport (HTX) slots.

The HTX bundle combines an intellectual property (IP) core for HTX compliant connectivity, an FPGA-based HTX acceleration card and a comprehensive software-programming environment.

The solution, part of Celoxica's family of Accelerated Computing products, enables customers to immediately leverage the benefits of algorithm acceleration using FPGA based coprocessors and high bandwidth HyperTransport communications.

The Celoxica RCHTX acceleration card includes two Xilinx Virtex 4 FPGA devices, 24Mbyte of dedicated QDR SRAM, and a range of I/O.

The main coprocessor FPGA is a high density 16 million gate device that can be reprogrammed by the user to accelerate compute intensive algorithms.

The second FPGA is configured as a bridge, containing an HTX IP core developed and licensed by Celoxica.

This bridge FPGA and IP provide the HyperTransport interconnect between the FPGA coprocessor and the entire host processor system and memory space.

Enabling the HTX solution, Celoxica's DK Design Suite delivers an IDE and compiler for software programming of the FPGA coprocessor.

DK allows HPC programmers to use familiar software languages and legacy code in the development of hardware accelerators.

Celoxica's technology compiles high-level, C-based code directly to the user FPGA device, eliminating the need to recode complex and proprietary algorithms into a low level hardware description language.

A board support package (BSP) and software API is provided for the RCHTX card to further streamline the design flow.

As demands drive data centre growth and complexity, HPC systems (supercomputers and clustered servers) are continuously being pressed to deliver higher compute performance within power and space constrained environments.

The low latency, high bandwidth interconnect provided by HyperTransport coupled with Celoxica's software programming environment for FPGA hardware enables HPC programmers to exploit FPGAs as parallel coprocessors that deliver orders of magnitude higher performance with little or no impact on existing power and floor space budgets.

"Three things have opened the door to making FPGA co-processing a reality today: the continued sise and speed improvements of FPGA silicon; the availability of high-bandwidth interfaces such as HyperTransport; and the advent of reliable compiler technology from software code directly to FPGA hardware", said Jeff Jussel Vice President of Marketing and General Manager of the Americas for Celoxica.

"Today, customer benchmarks demonstrate that our Accelerated Computing solutions deliver massive performance/power advantages for a wide range of compute intensive applications".

"HyperTransport technology and AMD64 technology with Direct Connect Architecture can provide a tightly coupled coprocessor expansion capability and address the communications bottleneck that has negatively impacted compute offload to coprocessors in other solutions", said Mike Goddard, Director, Advanced Technology Planning and Performance Labs, AMD.

"Coupling this with an easy-to-use programming environment, integrated card solution, IP and advances in FPGA technology makes this a successful example of Celoxia's valued support of AMD's Torrenza initiative".

Celoxica's HyperTransport solution complements its existing Accelerated Computing products, which provide compiler and hardware interface support to enable FPGA-based coprocessing for a wide range of HPC solutions.

Celoxica's RCHTX card is priced at $15,000 in single quantities and along with Celoxica compiler and HTX interface is available for immediate delivery.

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