Array-based SoCs boosts speed and density

The 0.18-micron CX5000 family of late-stage-programmable advanced gate array ASICs delivers significant increases in speed, gate count, memory and I/O.

Chip Express reckons it has raised the bar for late-stage-programmable advanced gate array ASICs with its new 0.18-micron CX5000 family, which delivers significant increases in speed, gate count, memory and I/O.

Moving to 0.18-micron geometry has allowed the company to introduce two new CX5000 product lines: the System Slice which provides a maximum of 1.8M usable gates and 2.5Mbit of memory, and the Memory Pig which delivers over 4.5Mbit of fast SRAM.

The CX5000 System Slice is designed to be the SoC platform gate array of choice, offering a range of eight options.

At the low end, the 189-pad CX50041 delivers 44K gates and 64Kbit fast SRAM/ROM.

The largest device, the 1089-pad CX51761, has 1.8M gates and 2.6Mbit memory plus many useful PLL and DLL macros.

Comments Doug Bailey, Vice President of Marketing with Chip Express, "The move to field-proven, high-reliability 0.18-micron processing means that we are delivering more true ASIC gates than any FPGA, and more fast I/O than any gate array.

With minimal NRE and dramatically reduced mask costs, this makes the new Chip Express CX5000 family a true standard cell alternative".

For memory-loaded designs, Chip Express has configured a second CX5000 product line, known as the Memory Pig.

Available in four versions, and again including combinations of PLLs, DLLs and high-speed I/O cells, Memory Pig devices are available with between 1.0 and 4.5Mbit of memory with a memory to logic gate ratio of over 500%.

Explains Bailey, "Gartner research shows - and our own customer base confirms - an ever-increasing appetite for memory.

We developed the Memory Pig specifically to satisfy the needs of those SoC and communications device designers who have enormous memory requirements".

Chip Express' CX5000 advanced gate array family runs at an impressive 200MHz.

The architecture means that the limiting factor on speed is power consumption, not gate delay, and Bailey argues that constrained logic areas will run much faster.

"Chip Express is conservative with its performance figures", he comments.

"The CX5000 product can easily support high-speed serdes, DDR memory interfaces and other high-performance IP".

Bailey continues, "By introducing our new 0.18-micron family now, we are delivering on our promise to develop two significant new technologies in two years.

Our System Slice and Memory Pig 0.18-micron products demonstrate that we are continuing to provide high-performance, cost-effective solutions for those designers searching for a viable alternative to expensive standard cell or slow, bulky FPGAs".

The CX5000 System Slice preliminary libraries are available now for download from the Chip Express website for customers targeting System Slice design handoffs in June 2003, with production silicon in September 2003.

Chip Express will begin accepting Memory Pig design handoffs in September.

Design NREs range from $35,000 to $100,000 depending on the design service needs of each application.

Unit pricing for devices at a 100,000/year run rate vary from under $2 to about $60 subject to device size, packaging and test requirements.

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