Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: ChipX | Subject: CX5000 family
Edited by the Electronicstalk Editorial
Team on 26 June 2003
Modular gate arrays point way to
structured ASICs
With its recently launched 0.18-micron CX5000 family, Chip Express reckons it is delivering the optimum balance of density, flexibility and memory.
Structured ASICs were one of the hot topics at DAC this year, with a host of vendors partnering with Synplicity to create an optimised design flow solution in response to customers who are choosing this approach over slow, bulky and expensive FPGAs, or traditional, inflexible and high NRE cost standard cell devices With its recently launched 0.18-micron CX5000 family, Chip Express - the originator of the modular gate array which is the technology behind the reality of structured ASICs - reckons it is delivering the optimum balance of density, flexibility and memory
This article was originally published on Electronicstalk on 29 Apr 2003 at 8.00am (UK)
Related stories
Array-based SoCs boosts speed and density
The 0.18-micron CX5000 family of late-stage-programmable advanced gate array ASICs delivers significant increases in speed, gate count, memory and I/O.
Libraries ease switch to structured ASIC design
Chip Express has endorsed Synplicity's Synplify ASIC software within its structured ASIC flow.
Comments Doug Bailey, VP marketing at Chip Express: "There are many product offerings in the market coalescing around the Structured ASIC banner.
Some are aimed only at FPGA conversion, and trade off logic density, flexibility and device speed to match the FPGA architecture.
However, we consciously developed the fasted and densest logic possible and we target our structured ASICs firmly as an alternative to standard cell technology.
Further reading
Structured ASIC DSPs outperform standard cells
Chip Express has added a high-performance DSP capability to its entire structured ASIC product line.
Another hat in the ring
Structured ASICs offer a new option for designers needing to provide digital signal processing functions, says Doug Bailey, VP Sales and Marketing at ChipX.
We prefer to solve the FPGA compatibility problem with EDA software".
The logic module architecture developed by Chip Express is inherently very efficient, so the Santa Clara company's new 0.18-micron CX5000 family can more than match competitors' 0.13-micron cost and core logic performance.
For example, the CX5000 System Slice delivers 1.7M useable gates with 2.5Mbit of memory, whereas the CX5000 Memory Pig delivers up to 546K useable gates and over 4.5Mbit of memory.
By remaining - for the present - with proven 0.18-micron process technology, Chip Express also ensures that its products are reliable, cost-effective and deliverable.
The company is in the process of designing a completely new architecture for a 0.13-micron introduction in 2004, which will avoid entirely the copper failure mode problems that other makers are experiencing at these small geometries.
Chip Express has also avoided the trap of limiting its customers to a platform-based technology.
Says Bailey: "The important issue is flexibility.
At first glance, platform-based designs using a collection of hard or soft IP may look attractive.
However, for this approach to be successful, the silicon vendor must second-guess the requirements of its entire customer base - an impossible task.
The result is that customers do not have the same degree of design flexibility, and end up paying for functions that they do not require".
Concludes Bailey: "This is an interesting time for the IC industry, with technology and economic factors combining to define a new sector, named Structured ASIC.
Chip Express is leading this new sector in performance, cost-effectiveness and reliability".
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