Structured ASIC DSPs outperform standard cells

Chip Express has added a high-performance DSP capability to its entire structured ASIC product line.

Chip Express has added a high-performance DSP capability to its entire structured ASIC product line.

By creating core logic optimised to take advantage of Synopsys' popular DesignWare library datapath generators, Chip Express is enabling designers to achieve near cell-based ASIC performance from Chip Express' structured ASIC technology.

Designers using Chip Express structured ASICs can automatically realise significant gains in performance and logic efficiency by having their register transfer level (RTL) DSP designs compiled using Synopsys' Design Compiler and DesignWare library.

"Our structured ASIC core logic was developed with performance in mind", said Steve Bateman, Vice President of Engineering at Chip Express.

"Each logic element can be configured into a variety of primitive cells suitable for synthesis.

We've optimised our combinational cells to take advantage of Synopsys' DesignWare library to generate high-performance and area-efficient adders, multipliers and other datapath and DSP components".

Chip Express' 0.18um CX5000 DSP performance now rivals 0.18um standard cell.

Bateman indicated that a recent test showed a 32bit multiplier using CX5000 taking just 3.6ns, compared with a widely used 0.18um standard cell's propagation delay of 3.0ns, and vastly better than the fastest 0.13um FPGA at over 11ns.

"A factor of three performance advantage over FPGA is an important innovation", added Bateman.

"Closing timing in modern FPGAs can be a real chore, so we expect many designers to focus on structured ASIC for production, using FPGA for algorithm verification only".

"DesignWare Library has been the technology of choice for DSP implementation in standard cell for many years", said Ed Bard, Director of Marketing for Synopsys' DesignWare Library.

"Because of the work that Chip Express has done to optimise their core logic cells to take advantage of DesignWare library, we expect that designers will see performance increases in their DSP and other arithmetically intensive designs targeting the Chip Express structured ASIC product families".

Designers with a current Synopsys DesignWare library and Chip Express structured ASIC licences, have immediate access, for no additional charge, to the high-performance DSP capability.

Chip Express can also provide RTL compilation services using Synopsys Design Compiler and DesignWare library for RTL handoff customers.

Back to top