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Product category: Microprocessors, Microcontrollers and DSPs
News Release from: ChipX | Subject: Structured ASICs
Edited by the Electronicstalk Editorial Team on 02 April 2004

Another hat in the ring

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Structured ASICs offer a new option for designers needing to provide digital signal processing functions, says Doug Bailey, VP Sales and Marketing at ChipX.

DSP is probably one of the most used technologies ever developed Products from cellphones to DVD players, to MP3 players, PCs, GPS receivers, wireless LANs and pretty much any other communications or media system use DSP to discriminate signals from noise, compress signals to fit a channel or condition the output of one system to the input of another

Implementation styles have morphed over time from the clunky single 16bit MAC chips in 48-pin aircraft-carrier-style ceramic DIPs to sleek, low-profile chip carriers hiding gigahertz programmable processors.

But the mathematics remains the same: multiplications and additions, and lots of them.

The market is burgeoning and as it grows, new opportunities spawn new companies and initiatives aimed at satisfying the performance goals and application diversity.

The obvious world champion of DSP is TI with its dominant position in the programmable DSP space.

TI outsells all other programmable pretenders by an order of magnitude.

The FPGA vendors, who are always aggressively pursuing design wins in hot markets, have merged their communications-based technology platforms with hard-wired multiplier blocks to create viable DSP algorithm development platforms and ASIC verification hardware.

Although FPGAs still suffer from poor performance in spite of their advanced technology and high price, their flexibility and reprogrammability make them hard to beat for low-volume systems with DSP needs.

It turns out, however, that the biggest market for DSP technology is as hard-wired blocks in embedded system ASICs and ASSP devices.

These chips are the low-cost workhorses of the fixed-function systems that we use to communicate with and to entertain ourselves.

By hard wiring the multiplications and additions and by carefully tuning the number of expensive multipliers required, designers can optimise their silicon cost to a fraction of the cost of a programmable DSP or configurable FPGA solution.

However, as has been widely publicised over the last year or so, the number of ASIC design starts is falling rapidly due mainly to the NRE cost of making an ASIC.

The costs are driven by the exponential growth in tooling costs, but also manifest themselves in the cost of designing and verifying increasingly complex systems.

For these reasons, system architects have been caught on the ropes by FPGAs that are beyond their weight class in performance and price and by programmable DSPs that require exotic DDR subsystems to feed gigahertz instruction sequencers.

The introduction and formation of structured ASIC technology provides designers with a new option.

ChipX (until recently known as Chip Express) has developed a 0.18um structured ASIC technology that approaches the performance of traditional standard-cell ASIC technology of a similar geometry but with the low NRE, fast time to market and easy physical implementation inherent in the structured ASIC genre.

ChipX' technology differs from structured ASIC technology from other companies because it is a "medium grained" structure.

The coarse grained technologies attempt to emulate FPGAs and have large logic modules with poor performance, and the fine grained technologies are very flexible, but require 10 or more programmable layers making the NRE high and reducing the time to market benefits.

The ChipX module has about 12 transistors available.

The module is programmed using two metal layers by depositing a template of metal onto the transistors that configures library elements that look very much like a standard cell library.

Not only does this mean that several AND/NAND/NOR and other primitives are available to the standard ASIC synthesis tools, but also more complex cells such as flip-flops.

By combining modules into larger structures, critical DSP components such as half-adders and full-adders are built efficiently.

Owing to the compact nature of the cells there is very little performance differential between a ChipX implementation and a true standard cell DSP approach.

If we compare the speed and gate count of various different functions in 0.18mm standard cell, ChipX CX5000 structured ASIC and the fastest speed grade of Xilinx Virtex II, (a 0.13mm device) we see that whereas an 8 x 8 multiply function runs at 1.75ns and takes 860 gates in standard cell, as a ChipX implementation it is comparable at 2.15ns, 940 gates.

In the Xilinx part it runs at 3.07ns and consumes 4000 gates.

For a 32 x 32 five-stage multiply function, standard cell comes in at 1.29ns and 17,000 gates.

The ChipX Structured ASIC equivalent runs at 1.35ns and takes 17,000 gates, but the Xilinx part crawls along at 4.92ns and takes 21,000 gates.

A ChipX CX5000 32 x 32 36bit MAC actually takes 3000 fewer gates than the standard cell version (15,000 compared with 18,000 - Xilinx uses 21,000) More information on the derivation of the competitive information, the log files and the backup data are available from the ChipX website for those who would like to know more.

Also available are the ChipX CX5000 design libraries, which can be downloaded and used to test the performance of any DSP VHDL/Verilog design.

Although it's too early to crown a new champion, and whether or not anyone in the DSP world could ever hold that title "undisputed", DSP engineers now have another choice.

Take a look, inform yourself of the capabilities of ChipX' structured ASICs and add our technology to your toolbox of DSP solutions.

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