Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: ChipX | Subject: CX6000 family
Edited by the Electronicstalk Editorial
Team on 06 July 2005
Structured ASICs have a bit on the side
The latest addition to ChipX' extensive structured ASIC product portfolio accelerates time to market and reduces risk by integrating silicon proven IP subsystems into the structured ASIC fabric.
New from ChipX is the CX6000 family of structured ASICs Fabricated in a high-performance eight-metal 0.13um process, the latest addition to ChipX' extensive structured ASIC product portfolio accelerates time to market and reduces risk by integrating silicon proven IP subsystems into the structured ASIC fabric
This article was originally published on Electronicstalk on 29 Apr 2003 at 8.00am (UK)
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Array-based SoCs boosts speed and density
The 0.18-micron CX5000 family of late-stage-programmable advanced gate array ASICs delivers significant increases in speed, gate count, memory and I/O.
Libraries ease switch to structured ASIC design
Chip Express has endorsed Synplicity's Synplify ASIC software within its structured ASIC flow.
The first 12 devices available in this new product family, the CX6200 series, integrate an industry-standard PHY for USB 2.0 high-speed On-The-Go (OTG) applications.
ChipX will supply a single-cycle per clock instruction 80515 processor capable of up to 200MHz operation, and a USB controller proven to work with the PHY to customers through IP partnerships.
The combination of PHY and controller has achieved USB-IF compliance in silicon.
Further reading
Modular gate arrays point way to structured ASICs
With its recently launched 0.18-micron CX5000 family, Chip Express reckons it is delivering the optimum balance of density, flexibility and memory.
Structured ASIC DSPs outperform standard cells
Chip Express has added a high-performance DSP capability to its entire structured ASIC product line.
Another hat in the ring
Structured ASICs offer a new option for designers needing to provide digital signal processing functions, says Doug Bailey, VP Sales and Marketing at ChipX.
"Normally, designers seeking to build USB capability into an ASIC must purchase a PHY, a controller, and a processor, integrate them into their design, develop the software, then run the entire solution through compliance testing", explains Elie Massabki, Vice President of Marketing with ChipX.
"This process is arduous, time-consuming and full of risk, since the various IP blocks may not communicate well".
"By providing our customers with a complete, compliance-capable solution, we can reduce their chip integration effort, shorten their development cycle and maximise their chance of design success".
The CX6200 series is ideal for PC peripheral, imaging, consumer, security and a variety of industrial applications.
New CX6200 products also enable profitable access to highly segmented markets using the SideChip approach.
A SideChip is a structured ASIC that resides next to a main ASIC and provides integration relief and flexibility to a system architecture.
In a growing number of systems where standards are changing and markets are segmented, designers regularly need to expand the capabilities of the system but cannot afford to respin the main system chip or build a new chip for each individual market.
By mounting additional capabilities on a ChipX SideChip with an embedded USB interface, designers can meet changing market requirements and extend the life of an existing system with minimal effort.
The new CX6000 family uses ChipX' silicon-proven X-Cell architecture.
The highly granular and efficient architecture delivers higher gate densities and much lower device costs when compared with programmable devices in smaller geometries.
This new ChipX product family can be customised in two, three or four layers of metal depending on the customer's priority in terms of density and time to market.
The CX6000 family is also equipped with configurable I/Os, capable of a wide range of capabilities including LVTTL, LVCMOS, SSTL18/2/3, HSTL, LVDS, LVPECL, XOSC, PCI, PCIX and double datarate.
The I/Os can be programmed with a number of parameters and can be individually configured as input, output, bi-directional, power or ground.
The new CX6200 product line offers 140,000 to 1.8 million ASIC gates, up to 1.2Mbit of embedded high-density SRAM and a maximum operating frequency of 250MHz.
It also adds four configurable, low-jitter PLLs with output frequency from 10MHz to 1GHz.
Tested prototypes can be delivered in as little as 4 weeks.
CX6200 device prices start at under $5 in 100,000 unit volume.
Customer designs can be accepted now and production units are expected in Q4 2005.
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