Product category:
Microprocessors, Microcontrollers and DSPs
News Release from: ChipX | Subject: CX6100 family
Edited by the Electronicstalk Editorial
Team on 18 October 2005
Structured ASICs take PCI Express
onboard
New from ChipX, the CX6100 family of structured ASICs is the latest addition to the company's growing portfolio of structured ASICs with embedded IP.
New from ChipX, the CX6100 family of structured ASICs is the latest addition to the company's growing portfolio of structured ASICs with embedded IP Fabricated in a high performance, eight-metal 0.13um process, the CX6100 devices accelerate time-to-market and eliminate many of the risks associated with traditional standard cell ASIC development by integrating a silicon-proven PCI Express (PCIe) PHY core
This article was originally published on Electronicstalk on 9 Jun 2006 at 8.00am (UK)
Related stories
Structured ASIC development takes PCIe onboard
A new development kit for the CX6100 family of structured ASICs helps designers lower their design risk, reduce verification time and dramatically shorten their development cycle.
Array-based SoCs boosts speed and density
The 0.18-micron CX5000 family of late-stage-programmable advanced gate array ASICs delivers significant increases in speed, gate count, memory and I/O.
At the same time, the new product family offers designers a significantly higher performance, lower power alternative to FPGA-based solutions.
The 12 devices in the new CX6100 structured ASIC family support a wide range of applications in computing, storage, instrumentation and networking.
The embedded PCIe PHY is compliant with the current 1.1 version of the specification and is available in one, four and eight lane options.
Further reading
Libraries ease switch to structured ASIC design
Chip Express has endorsed Synplicity's Synplify ASIC software within its structured ASIC flow.
Modular gate arrays point way to structured ASICs
With its recently launched 0.18-micron CX5000 family, Chip Express reckons it is delivering the optimum balance of density, flexibility and memory.
Structured ASIC DSPs outperform standard cells
Chip Express has added a high-performance DSP capability to its entire structured ASIC product line.
Along with the embedded PHY, ChipX is offering an optional PCIe-compliant controller.
The PHY offers complete PIPE interoperability for customers wishing to use their own PCIe controller.
"The electronics industry is quickly migrating to PCI-Express, which is quickly becoming the de-facto standard for PCs and embedded applications", said Wouter Suverkropp, Director of Strategic Marketing at ChipX.
"But the ongoing evolution of the standard, forces designers to rapidly bring to market new iterations of their products to maintain compliance".
"With an FPGA, you compromise latency, system speed and power".
"With a standard cell ASIC, development cycles are long and PHY integration risk is high".
"By embedding a silicon-proven PCIe PHY that is supported by compliance testing and an optional controller, the CX6100 family eliminates the complexity and risk associated with integrating IP from multiple vendors and allows designers to rapidly develop solutions that keep pace with the evolving standard".
With the optional PCIe 1.0a compliant controller, designers can quickly develop root port, bridge and endpoint designs.
The controller supports one, four or eight lanes, up to eight VCs and up to six BARs.
It features configurable retry buffers and support for up to 4Kbyte payload sizes.
The controller is supplied complete with simulation models, driver software examples and all documentation.
The new CX6100 family is built on ChipX's silicon-proven X-Cell architecture.
This fine-grain, efficient architecture delivers higher gate densities and lower device costs when compared with programmable devices in smaller geometries.
This new ChipX product family can be customised in two, three or four layers of metal, depending on the customer's priority in terms of density and time to market.
The 12 devices in the CX6100 family offer densities ranging from 240,000 to 1.8 million ASIC gates, up to 1.1Mbit of embedded SRAM and maximum operating frequencies up to 250MHz across the die.
Four on-chip, configurable, low-jitter PLLs support output frequencies from 10MHz to 1GHz.
Customers can receive tested prototypes in as little as four weeks.
Pricing for the CX6100 devices starts under $7 in volumes of 100,000.
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