Product category:
Intellectual Property Cores
News Release from: ChipX | Subject: CX6000 structured ASICs
Edited by the Electronicstalk Editorial
Team on 23 October 2006
Memory PHY puts ASICs in touch with
SDRAM
Complete DDR/DDR2 SDRAM solution with speeds up to 667Mbit/s combines a DDR/DDR2 PHY and DDR/DDR2 SDRAM controller cores for use on all CX6000 structured ASIC products.
ChipX and Northwest Logic offer a complete DDR/DDR2 SDRAM solution with speeds up to 667Mbit/s, including a DDR/DDR2 PHY and DDR/DDR2 SDRAM controller cores for use on all CX6000 structured ASIC products All DDR/DDR2 SDRAM chip designs require close integration of the physical interface (PHY) with both the chip process and the memory controller core in order to meet tight memory timing requirements
This article was originally published on Electronicstalk on 29 Apr 2003 at 8.00am (UK)
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The 0.18-micron CX5000 family of late-stage-programmable advanced gate array ASICs delivers significant increases in speed, gate count, memory and I/O.
Libraries ease switch to structured ASIC design
Chip Express has endorsed Synplicity's Synplify ASIC software within its structured ASIC flow.
Third-party PHY designs often require extensive custom engineering to meet performance specifications of a specific process, and often do not integrate well with the target memory controller core, leading to a significant challenge for the chip designer.
The ChipX solution solves this design challenge by offering a DDR/DDR2 PHY design built entirely out of logic cells (X-Cells) on the CX6000 130nm family of structured ASIC products.
This PHY has been integrated and verified with the configurable memory controller cores from Northwest Logic.
Further reading
Modular gate arrays point way to structured ASICs
With its recently launched 0.18-micron CX5000 family, Chip Express reckons it is delivering the optimum balance of density, flexibility and memory.
Structured ASIC DSPs outperform standard cells
Chip Express has added a high-performance DSP capability to its entire structured ASIC product line.
The ChipX DDR/DDR2 PHY can be placed next to any CX6000 I/O bank and supports any bus width in 8bit increments.
Because the PHY design is implemented as an overlay and does not reside in the basic gates, there is no penalty if it is not placed.
The Northwest Logic DDR and DDR2 memory controller cores provide extremely high bus efficiency using request reordering, bank management and look-ahead processing.
The cores can also be configured during design or real-time to work with any memory configuration.
Northwest Logic also provides separate ECC, read-modify-write and multiport front-end addon modules to enable each design to be optimally configured.
The cores support the very high memory clock rates and have a minimal gate count.
"The ChipX DDR/DDR2 PHY solution is unique, because customers get the maximum performance without any integration effort, yet don't pay any penalty for the flexibility this design offers", said Wouter Suverkropp, Director of Marketing at ChipX.
"If a DDR/DDR2 SDRAM solution is required, the DDR/DDR2 PHY and memory controller core are placed in the CX6000 fabric as a firm macro with guaranteed performance".
"If you don't need such a solution, you just use the gates for something else, without any overhead".
"The integration of the ChipX DDR/DDR2 PHY with the Northwest Logic DDR and DDR2 memory controllers provides a high-performance, easy-to-use SDRAM solution", said Brian Daellenbach, President of Northwest Logic.
"Customers can use this solution to quickly develop and bring to market chips that incorporate a DDR/DDR2 SDRAM interface".
The ChipX DDR/DDR2 PHY is shipping in customer silicon today, and is available as a macro on any CX6000 130nm structured ASIC, including an extensive range of products with USB 2.0 HS OTG and PCI Express.
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