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News Release from: Cast | Subject: APS-DSP
Edited by the Electronicstalk Editorial
Team on 29 May 2007
32bit cores gain DSP companions
Cast now offers a digital signal processing coprocessor for the APS family of 32bit processor IP cores.
Cast now offers a digital signal processing (DSP) coprocessor for the APS family of 32bit processor IP cores Introduced a year ago, the APS family brings 32bit processing power to designers more familiar with 8051s and other 8bit microcontrollers
This article was originally published on Electronicstalk on 18 Apr 2007 at 8.00am (UK)
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"Customers have found that APS delivers a real sweet-spot combination of fast processing, small area, and low power that's perfect for many applications", says Hal Barbour, President of Cast.
"This easy DSP coprocessor means designers can now succeed in an exploding market where products need to have voice recognition, streaming video, or other slick features just to get noticed".
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The APS-DSP and the APS family of processors have been developed by Cast partner Cortus, in France.
The coprocessor is available now as an integrated addon to the APS2 and APS3 processor cores, and is ready for implementation in ASICs, structured ASICs or FPGAs.
The APS-DSP is a fixed point, general purpose, 16bit extension to the APS family of processors.
It expands the APS instruction set with special DSP functions, and adds additional processing and memory interface hardware to significantly improve performance for complex arithmetic calculations.
The patented coprocessor interface built into APS processors enables tight integration and parallel operation of the DSP and main CPU functions.
This means instructions complete in a single cycle, with the DSP coprocessor and the main processor executing instructions at the same speed, and with out-of-order instruction completion.
The coprocessor adds three arithmetic logic units (ALUs) operating in parallel, improving performance by enabling one arithmetic operation and two address calculations on every clock cycle.
It adds two memory interfaces for greater memory bandwidth, and uses a Harvard bus architecture for simple memory design.
A bit-reverse arithmetic feature facilitates certain DSP calculations, and special zero overhead loop (ZOL) hardware enables smarter, more efficient data processing.
Instructions for the APS-DSP are written in efficient assembler language using a simple, straightforward, set of constructs.
Provided macros make it easy to work with the DSP routines from the C and C++ programming environments of the APS processors.
An included library offers precoded solutions for typical DSP challenges such as Fast Fourier Transforms (FFTs) and common architectures for both Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) digital filters.
Designers can use these specific solutions without having the detailed DSP expertise necessary to implement the algorithms from scratch.
The 16bit APS-DSP works with both members of the APS family, the 32bit APS2 for high performance, and the 16/32bit APS3 for dense code.
Designed primarily as 8051 upgrades for deeply embedded systems, APS cores offer significantly more capability and speed than 8bit processors while conserving silicon area, power, and cost compared with popular 32bit processors.
Multiple customers have selected APS over the past year, and the first customer designs are nearing production.
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