Product category:
Design and Development Software
News Release from: Carbon Design Systems | Subject: DesignPlayer
Edited by the Electronicstalk Editorial
Team on 27 August 2004
Virtual system debugs real device
software
Carbon Design Systems has integrated its DesignPlayer engine with Virtutech's Simics Instruction Set Simulator (ISS).
Carbon Design Systems has integrated its DesignPlayer engine with Virtutech's Simics Instruction Set Simulator (ISS) This will enable customers with processor-based designs to execute operating systems and application-level software on a fast and accurate model of a chip or system
This article was originally published on Electronicstalk on 22 Apr 2004 at 8.00am (UK)
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Package accelerates verification regression
New enhancements to DesignPlayer will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain.
Acceleration for VHDL and mixed-language designs
Carbon Design Systems has added VHDL and mixed language (VHDL and Verilog) support to its product line.
This integration allowed Sun Microsystems to boot its Solaris operating system on a Simics-DesignPlayer model of its design.
"Booting an operating system on an RTL-accurate model of a design is now possible without a hardware emulator or first silicon", commented Steve Butler, President and CEO of Carbon.
"The Virtutech-Carbon combination provides both the speed and accuracy to debug real software on a virtual system".
Further reading
SoC tool suite becomes design language agnostic
SOC-VSP complements the power of ARM RealView SoC Designer by importing Verilog and/or VHDL (RTL) into a RealView SoC development environment.
Automatic compilation speeds model development
Astute Networks has successfully validated both the embedded firmware and hardware for its next generation storage processor chip using Carbon's VSP product.
"For the first time, a design's RTL implementation can replace an ideal model without sacrificing performance", remarked Peter Magnusson, Founder and CEO of Virtutech.
"Simics can now be used for architecture development, performance modeling, and software validation on the RTL hardware model".
Carbon's SpeedCompiler software creates a high-performance engine - DesignPlayer - from a design's synthesisable Verilog and/or VHDL.
The DesignPlayer-Simics integration allows one or more DesignPlayers to be called directly from the Simics ISS.
Unlike a traditional simulator, DesignPlayer is a simulation client - it doesn't control system time.
The surrounding simulation environment - Simics - controls system time, which greatly minimises the integration complexity.
The Simics-DesignPlayer combination can run millions of instructions per second, as DesignPlayer only executes when it is called by the Simics ISS.
This single master-of-time architecture removes the multiple-master performance bottleneck inherent in cosimulation.
DesignPlayer can represent one or more chips and multiple engines can represent a system that encompasses hundreds of millions of gates.
DesignPlayer is a soft-model that is accurate to the hardware-cycle and register accurate.
Unlike behavioural models or C models generated from an ideal specification, DesignPlayer behaves exactly like the hardware with all its errata.
Hardware designers now have the cycles they need to run complete regression suites before chip tapeout.
Software designers can finally test and debug their code on a high performance, cycle accurate, linkable model.
Customers get an executable specification that contains the silicon errata for system integration and test.
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