Product category:
Design and Development Software
News Release from: Carbon Design Systems | Subject: SOC-VSP
Edited by the Electronicstalk Editorial
Team on 22 June 2006
Replay function speeds software
validation
Carbon Design Systems will introduce major new functionality for its SOC-VSP product line at this year's Design Automation Conference.
Carbon Design Systems will introduce major new functionality for its SOC-VSP product line at this year's Design Automation Conference ESL simulation environments typically contain models at different levels of abstraction, accuracy and performance, including: behavioural, instruction-level, transaction-level, cycle-accurate and bus transactors that maintain state information
This article was originally published on Electronicstalk on 7 Dec 2005 at 8.00am (UK)
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SoC tool suite becomes design language agnostic
SOC-VSP complements the power of ARM RealView SoC Designer by importing Verilog and/or VHDL (RTL) into a RealView SoC development environment.
SoC models are fit for system level design
Models from SOC-VSP software plug-and-play with the Platform Architect design environment from CoWare.
Developers validating software on a system model must iterate through all their previously validated code when adding new functionality or debugging problems that may have occurred hours into a simulation.
Although this isn't a performance issue if all the simulation models are homogeneous at the highest levels of abstraction, it is a throughput issue as accuracy is introduced to the system model through IP integration and RTL implementation.
Carbon's Replay removes this performance barrier to incorporating RTL into a heterogeneous modelling environment by enabling rapid software iterations through validated code and interactive software debug, while maintaining the underlying cycle-accuracy.
Further reading
Model integration finds more bugs with MIPS
Carbon Design Systems has integrated its models with the MIPSsim instruction set simulator and software debugger to provide complete validation for MIPS-based SoCs.
Package accelerates verification regression
New enhancements to DesignPlayer will allow it to be seamlessly plugged into hardware regression environments, be driven by a variety of testbenches, and provide a 10x or greater performance gain.
"By eliminating the need to rerun the 'Carbonised' hardware model for each software iteration, simulation throughput can be boosted by one to two orders of magnitude", said Alan Swahn, Vice President of Marketing at Carbon Design Systems.
"Our Replay technology enables RTL to be included in an ESL environment, while maintaining performance for software developers".
Software developers commonly iterate through previously validated code many times in the design and validation process.
The underlying system model of the hardware components is usually high-performance, but not cycle-accurate.
Unfortunately, this limits the degree to which software drivers and embedded firmware can be validated before a physical prototype is available.
This delays software development starting in earnest until late in the design cycle.
Replay is a novel idea to break this performance-accuracy logjam.
"Carbonised" cycle-accurate RTL models can record incoming bus traffic and response for an initial simulation and save the model state information at specified intervals.
During the next software execution iteration, the Carbonised model is stimulated from other abstract components in the system and replays its saved response at very high speed until the last valid checkpoint, at which time the Carbonised model restores its state and simulates normally from that point forward.
Replay mode will detect any inputs that don't match in sequence or value and automatically rollback to the previous checkpoint to ensure correct operation.
Replay performance enables interactive software debugging.
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