Product category:
Design and Development Software
News Release from: Carbon Design Systems | Subject: SOC-VSP for MIPSsim
Edited by the Electronicstalk Editorial
Team on 21 May 2007
Model integration finds more bugs with
MIPS
Carbon Design Systems has integrated its models with the MIPSsim instruction set simulator and software debugger to provide complete validation for MIPS-based SoCs.
Carbon Design Systems has joined the MIPS Alliance Programme (MAP), adding MIPS Technologies to its growing number of strategic partners Carbon has also integrated its models with the MIPSsim instruction set simulator and software debugger to provide a complete validation solution for MIPS-based SoC design
This article was originally published on Electronicstalk on 22 Apr 2004 at 8.00am (UK)
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The MIPS32 and MIPS64 RISC microprocessor architectures are industry standards and performance leaders within the embedded industry.
The alliance programme collaboration between Carbon and MIPS enables their customers to rapidly identify and fix bugs in both hardware and software.
"We're extremely pleased with the joint Carbon/MIPS solution", says Jim O'Connor, Senior Vice President of Engineering at iVivity.
Further reading
Acceleration for VHDL and mixed-language designs
Carbon Design Systems has added VHDL and mixed language (VHDL and Verilog) support to its product line.
SoC tool suite becomes design language agnostic
SOC-VSP complements the power of ARM RealView SoC Designer by importing Verilog and/or VHDL (RTL) into a RealView SoC development environment.
Automatic compilation speeds model development
Astute Networks has successfully validated both the embedded firmware and hardware for its next generation storage processor chip using Carbon's VSP product.
"This integration has enabled us to identify a number of hardware and software bugs in our next-generation SoC.
The 100% model visibility and fast runtime capability have enabled us to find and repair bugs five times faster than with our previous FPGA prototype methodology".
"The combination of Carbon's model generation technology with our simulation technology enables our customers to start with system-level development and debug much earlier", adds Jack Browne, Vice President of Marketing at MIPS Technologies.
"This integration enables a system-level approach to validate customer and third-party IP with our industry standard architecture".
"Our collaboration with MIPS will enable our customers to start their system integration tasks even earlier than was previously possible", remarks Rick Lucier, CEO of Carbon Design Systems.
"Presilicon system integration allows our joint customers to identify and fix problems early in the design cycle, and greatly reduce the amount of time required to bring up the system in the lab".
"It's a win/win solution when we can help our customers reduce costs and increase time to revenue".
Carbon software compiles Verilog and/or VHDL hardware descriptions into high speed software models.
As part of its collaboration with MIPS Technologies, Carbon has developed SystemC technology to link these Carbon models directly to the MIPSsim instruction set simulator and software debugger.
This direct integration allows the entire SoC to be quickly modelled and run in SystemC.
The MIPSsim instruction set simulator executes the embedded firmware and generates transactions for the hardware models.
Carbon's integration targets these transactions to the correct hardware component and executes the RTL behaviour.
Software developed and tested on the joint Carbon/MIPS model can be easily debugged, while hardware problems can be quickly diagnosed using Carbon's 100% design visibility, interactive API and VCD/FSDB waveform capability.
The ability to concurrently debug hardware and software enables issues to be identified and repaired much more quickly than with any other solution.
Carbon SOC-VSP software with virtual hardware model generation for MIPS Technologies' MIPSsim instruction set simulator is now publicly available.
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