Product category:
Design and Development Software
News Release from: CoWare | Subject: SPW 4.85
Edited by the Electronicstalk Editorial
Team on 04 October 2004
Verification for DSP designs in Matlab
CoWare and AccelChip have combined to provide an advanced design and verification flow for DSP designs that originate in Matlab.
CoWare and AccelChip have combined to provide an advanced design and verification flow for DSP designs that originate in Matlab The companies have integrated CoWare's DSP application design tool, SPW, with AccelChip's algorithmic synthesis tools to offer DSP design teams the ability to verify generated RTL code in Verilog or VHDL within the SPW environment
This article was originally published on Electronicstalk on 15 May 2008 at 8.00am (UK)
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"AccelChip provides Matlab-based algorithmic synthesis for FPGAs and ASICs by automatically generating VHDL or Verilog from Matlab algorithms".
"By partnering with CoWare, our mutual customers can now verify their algorithms at all levels of abstraction - Matlab, RTL and gate - within the context of the entire system".
"CoWare's SPW provides a full DSP system verification infrastructure that includes an extremely fast simulation engine".
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"The combination of AccelChip's automatic, algorithmic-based implementation flow and CoWare's DSP verification environment enables customers to have complete confidence as they implement their complex DSP designs", said Tom Feist, Vice President of Sales and Marketing, AccelChip.
"With the integration of SPW and AccelChip - one of the most innovative Matlab-based implementation technologies - design teams have access to fast and accurate DSP verification when implementing Matlab designs", said Mark Milligan, Vice President of Marketing, CoWare.
"Along with the enhanced Matlab simulation and analysis capabilities in the new SPW 5-XP, this integration highlights our commitment to supporting the technologies in the MATLAB ecosystem".
The integration between SPW and AccelChip DSP Synthesis lets designers using AccelChip's Matlab-based, algorithm synthesis flow verify each level of their design in SPW.
DSP designers typically start their design process in Matlab, the world's leading software for algorithm design.
The AccelChip DSP Synthesis product generates fixed-point Matlab from the original Matlab floating-point algorithm, and then synthesises RTL - either VHDL or Verilog - from the fixed-point Matlab.
SPW allows designers to simulate their floating-point Matlab algorithms.
After running the design through the AccelChip toolset, the designer can import the RTL generated from AccelChip into SPW to verify at the RTL level.
This approach provides a complete, system-wide verification of the complete signal processing design.
CoWare SPW - the DSP workbench - is a complete DSP application design platform featuring high performance simulation technology and an easily accessible, large library of 4000+ DSP application models.
SPW integrates with many leading tools supporting design flows using Matlab, C/C++, SystemC, Verilog/VHDL and Verilog-AMS.
Its up-to-date communications and multimedia libraries reduce time and effort for customers designing for standards like 3GPP, UWB or 802.11.
The AccelChip DSP Synthesis tool automatically generates synthesisable, cycle-accurate RTL models directly from Matlab M-files.
The tool's enhanced floating- to fixed-point conversion gives the designer much better control over trade-offs between performance, area, and accuracy.
AccelChip DSP Synthesis enables system-level verification of all components using libraries and math-based models, increases efficiency, and provides unheard of flexibility by allowing designers to explore architectural possibilities without ever touching their golden source.
CoWare SPW 4.85 featuring AccelChip application support is available to SPW customers today.
Future releases of SPW 5-XP for Windows will provide similar integration.
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