SystemC-based models speed ZSP design

CoWare and LSI Logic have developed ZSP SystemC-based models for use with the CoWare ConvergenSC design environment.

CoWare and LSI Logic have developed ZSP SystemC-based models for use with the CoWare ConvergenSC design environment.

LSI Logic developed cycle- and transaction-accurate SystemC-based models for each of the available ZSP cores (ZSP200, ZSP400, ZSP500, ZSP540 and ZSP600) and, through joint co-operation with CoWare, integrated the ZSP models into CoWare's extensive ConvergenSC Model Library.

The first deliverable of this ongoing relationship-the ZSP500 model-is available now.

"The ability to quickly and accurately model an SoC during the architecture phase is critical for bringing an optimised product, in terms of cost and performance, into the marketplace", said Rafi Kedem, Senior Director of Marketing of the LSI Logic DSP Products Division.

"Designers can select the appropriate DSP core from the software compatible family of ZSP cores to handle the signal processing and system control tasks".

"The collaboration with CoWare helps our customers to develop applications in the wireless, voice and multimedia segments while beating their performance and cost goals for these complex SoC designs".

"With ConvergenSC, the SoC designer can analyse and optimise the combination of the ZSP on-chip interconnect, the ZSP memory-subsystem, and the ZSP software in order to get the maximum system-level performance", said Mark Milligan, Vice President of Marketing, CoWare.

"These new models give designers using the ZSP cores even greater ability to differentiate their designs in competitive applications".

By running SystemC simulations and performance analysis in ConvergenSC with the new CoWare ZSP models, users can quickly determine the optimum architecture for their specific application and debug the interaction between software and hardware early in the design process.

The tools let customers perform detailed analysis of processor throughput and latency, as well as memory subsystem performance and bus analysis.

Analysis results can be viewed graphically and used to determine how a design and the application software could be optimised.

With the ability to measure the key parameters that affect processor performance, users can design better performing systems optimised around the LSI Logic ZSP cores.

The models are based on a jointly developed, high performance, fully instrumented integration of the LSI Logic ZSP Core Simulator in SystemC.

They also feature an additional cycle accurate model of the LSI Logic Memory Subsystem (MSS) - providing users the choice of using additional pre-verified IP from LSI Logic or developing their own custom memory subsystem-and include internal and external memory and Z.turbo TLM APIs for ease of use and system integration flexibility.

The models support multi-instance, multicore simulations and are integrated with the LSI Logic software tool chain for increased simulation performance and software debug ease of use.

CoWare's model for the LSI Logic ZSP500 is available now.

Models for LSI Logic's other ZSP cores will subsequently follow.

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