Model sets enable hardware verification

CoWare's platform-driven ESL design solution enables hardware verification, architecture exploration and software development on IBM PowerPC 440 and CoreConnect-based platforms.

CoWare has added two IBM model sets to its SystemC Model Library.

The IBM PowerPC 440 Processor Support Package and the IBM CoreConnect Bus Library consist of a set of SystemC models for PLB and DCR busses.

They are available with some sample PLB and DCR peripherals.

CoWare's platform-driven ESL design solution enables hardware verification, architecture exploration and software development on IBM PowerPC 440 and CoreConnect-based platforms.

With CoWare's solution, engineers can discover issues early in the design cycle, parallelise hardware and software development and reduce their design cycle.

"Design at the electronic system-level is essential to take optimum advantage of the IBM PowerPC 440's and IBM Core Connect's powerful capabilities in a product platform", said Richard Busch, Director of ASIC Products, Power Architecture Licensing and Cores, IBM Global Engineering Solutions.

"We're excited that our collaboration with CoWare provides our mutual customers with the right tools to help make these architectural decisions and start software development earlier in the design cycle".

"Consumer electronic products contain so much software now that having models available early, prior to the completion of the hardware platform, is essential", said Tom De Schutter, Marketing Manager, IP and Third-Party Relationships, CoWare.

"Software development needs to begin early in the highly-competitive consumer electronics market so that the design cycle can be reduced and the platform can be optimised quickly".

"Availability of the right architecture and software are today's main competitive differentiators".

The integration of the transaction-level SystemC IBM IP models into the CoWare tools offers users a fast simulation speed environment with an extensive set of configuration options.

This ensures that important design decisions can be optimised in the context of the full platform running the real software on the processors.

The right set of debug and analysis features boost hardware verification, architecture exploration and software development productivity.

This in turn reduces the design cycle and helps prevent over design of the target platform.

The result is a reduction in the final cost of the product.

IBM PowerPC 440 and IBM CoreConnect models are available immediately in the CoWare SystemC Model Library.

Back to top