Product category:
Communications ICs (Wired)
News Release from: Coresonic | Subject: LeoCore-1
Edited by the Electronicstalk Editorial
Team on 11 September 2006
Core architecture is optimised for comms
With a new type of processor architecture, Coresonic has developed a programmable baseband it reckons will revolutionise the communication industry.
Coresonic, a leading provider of baseband processor technology, has announced the LeoCore-1 programmable baseband processor SIP core With a new type of processor architecture, Coresonic has developed a programmable baseband that revolutionises the communication industry
This article was originally published on Electronicstalk on 11 Mar 2008 at 8.00am (UK)
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The LeoCore technology enables the developers of communication semiconductors to build more flexible solutions with less silicon area than fixed-function solutions.
Coresonic licenses the technology as a silicon intellectual property (SIP) core thereby enabling communication semiconductor vendors and module developers to implement this powerful technology in their designs.
"After years of research we have presented an architecture that achieves the best of two worlds, the flexibility of a programmable processor with the low cost and low power consumption of a fixed-function ASIC", says Dr Dake Liu, CTO and Cofounder of Coresonic.
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"This technology is truly a revolution for the industry".
Coresonic has also released the Coresonic Developer Studio, a fully fledged software development package that enables the designers to quickly acquaint themselves and develop with the LeoCore architecture.
The flexibility of the LeoCore technology makes it a great solution of a wide variety of wireless communication applications, including cellular handsets and modems for laptops and PDAs.
LeoCore-1 supports WLAN standards 802.11 a/b/g, GSM/GPRS/Edge, Bluetooth 1 and EDR, WiMAX and DVB-T.
Apart from enabling multimode devices, the flexibility of the LeoCore technology also shortens time to market for the customers who can integrate the LeoCore SIP Core and develop software in the matter of months.
The technology further eases maintenance with the capability of firmware upgrades instead of hardware changes.
Firmware upgrades also allows for longer product lifetimes.
"Datarate and mobility tradeoffs and different standards like 2G, 3G, Bluetooth, WLAN, GPS and digital-video broadcasting, are leading to multimode requirements, and topics such as the coexistence of different technologies must be solved".
"One crucial element for such a platform is a low power programmable modem processor", says Prof Dr Hermann Eul, President of Communication Solutions Group, Infineon Technologies.
The Coresonic LeoCore technology is based on a breakthrough processor architecture called SIMT (single instruction stream multiple tasks).
The architecture allows parallel tasks to be controlled by a single instruction flow, achieving a large degree of parallelism while reducing both hardware- and programming complexity compared with other parallel architectures.
Compared with VLIW-SIMD architectures the same performance is reached with much smaller program size and simpler control hardware.
Coresonic combines the revolutionary SIMT principle with an instruction set optimised for baseband processing.
An integral part of the architecture is a programmable on-chip network which secures efficient use of data memory as well as efficient integration of hardware acceleration blocks.
All in all, this has allowed Coresonic to build a processor highly optimised for baseband processing with a small silicon area and power consumption.
"A key point in our design philosophy has been to start from baseband processing algorithms and requirements, not from traditional computer architectures", Dake Liu adds.
For a WLAN a/b/g application, the LeoCore technology typically reduces the silicon area to between half the area to two-thirds of the area and uses a quarter of the power in comparison to other leading programmable solutions.
In comparison to a fixed-function solution the power consumption is similar but the silicon area is reduced to a third with Coresonic's solution.
Coresonic offers a set of development tools to ease evaluation and development with the LeoCore technology.
The Coresonic Developer Studio (CDS) is a development platform including a cycle-true and bit-true simulator as well as assembler and debugger.
In combination with libraries and firmware examples, this is a very good starting point for any customer interested in the LeoCore technology.
The CDS for LeoCore-1 can be licensed today.
A demonstrator board, based on an FPGA-implementation of the LeoCore-1, is also available for evaluation and development.
The LeoCore technology is best suited for multimode, mobile, wireless communication.
One typical application is a multimode laptop/PDA/cellphone modem capable of GSM/GPRS audio/data communication, Bluetooth, WLAN and WiMAX.
The LeoCore-1 programmable baseband processor, together with an RF front-end, an ADC/DAC and the MAC are all components needed for a complete multimode wireless communication solution.
Coresonic's ambition is to provide well-tested and verified IP blocks and are continuously working to improve the technology.
The LeoCore-1 IP core is fully synthesisable for most process technologies and delivered as a net list.
A prototype of the LeoCore-1 IP Core has confirmed the low silicon area and power consumption.
In a 0.18um CMOS process the complete baseband from ADC/DAC to MAC (excluding Viterbi accelerator) used 2.9mm2 silicon area and had an average power consumption at full load of 80mW for WLAN 802.11 a/b/g.
The technology has also been tested and verified based on commercial C-level baseband algorithms from a tier 1 customer.
The LeoCore-1 programmable baseband processor SIP core is now available for licensing and implementation by key customers.
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