PowerPC cores available as IP for CPLDs

Cypress Semiconductor and Eureka Technology have announced the immediate availability of Eureka's suite of PowerPC IP cores for the Cypress Delta39K family of complex programmable logic devices.

Cypress Semiconductor and Eureka Technology have announced the immediate availability of Eureka's suite of PowerPC IP cores for the Cypress Delta39K family of complex programmable logic devices (CPLDs).

Through the Cypress IP Oasis programme, the PowerPC cores become part of a total CPLD solution for high-end communications systems, including routers, switches, control plane processors, servers, and terminals.

The cores are optimised for use in Cypress's HDL-based Warp design tool, which integrates graphical capture, synthesis, fitting, simulation, and advanced design analysis capabilities.

"These IP cores from Eureka exemplify the growing support from third-party vendors for Cypress's Delta39K family and our commitment to provide our customers with a complete system solution", said Geoff Charubin, Cypress director of marketing.

"As our CPLDs become more flexible with the introduction of additional IP support, their synergy with other Cypress devices increases.

For example, designers can combine a Delta39K CPLD with a PowerPC core with our OC-48 PHY, No Bus Latency (NoBL) and DualPort memories, and Zero Delay Buffers (ZDBs) to build a LAN switch card solution".

"Eureka continues its drive to provide IP cores to Cypress's IP Oasis programme, reinforcing our own strategy to support programmable devices with silicon-proven and production-proven IP", said Simon Lau, president of Eureka Technology.

"We will continue our commitment to add to the growing library of CPU bus interface and system control function cores for the Delta39K devices, enabling designers to tackle design issues and speed their time-to-market".

The EP201 PowerPC Bus Master is designed to initiate read/write data transfers on the PowerPC CPU host bus.

It is typically connected to a DMA controller, bus snooping, or peripheral bus device such as PCI.

The EP100 PowerPC Bus Slave is designed to be a target for CPU or other bus master access.

It can be used as an interface between the CPU and the system's core logic, memory subsystem or peripheral device such as a PCI host bridge.

The EC300 PowerPC Arbiter arbitrates between multiple bus masters on the PowerPC bus.

All Eureka PowerPC cores are compatible with the PowerPC, 603, 740, 750 and MPC8260 microprocessors.

Also available to designers using the Delta39K family of CPLDs are the Eureka PCI bus cores and SDRAM controller core.

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