IP core enables 2.5Gbit/s serial links

Cypress Semiconductor has brought its Programmable Serial Interface (PSI) family of programmable PHY devices into the InfiniBand marketplace with the introduction of an InfiniBand IP core.

Cypress Semiconductor has brought its Programmable Serial Interface (PSI) family of programmable PHY devices into the InfiniBand marketplace with the introduction of an InfiniBand IP core.

The core can be implemented in the company's CYP25G01K100 PSI device, the world's only 2.5Gbit/s programmable PHY and one of the recently delivered devices in Cypress's family of programmable PHYs.

The InfiniPHY IP core is a point-to-point, integrated communications solution that enables the transfer of data over high-speed serial links - optical fibre, PCB traces and copper transmission lines - at up to 2.5Gbit/s.

When implemented in the programmable PHY, the core leaves approximately 50,000 gates for custom logic.

"This IP core ensures interoperability by supporting InfiniBand-compliant byte alignment and recognising link-training sequences", said Richard Kapusta, senior product marketing manager at Cypress.

"This highly-integrated solution results in significant savings in board real estate and power consumption".

The InfiniBand IP core features comma detect, 8B/10B encoder/decoder, 16bit-parallel/serial conversion in the transmit path, serial/16bit-parallel conversion in the receive path and clock-tolerance compensation logic.

"Cypress is ahead of other programmable logic vendors in providing a programmable InfiniBand solution", said Geoff Charubin, director of data communications marketing at Cypress.

"In the near future we will provide both 4- and 12-channel InfiniBand solutions.

Other companies will have to find partners or make acquisitions to provide the flexibility, customisation and integration that Cypress can deliver today".

A PSI device with the InfiniPHY IP core will provide complete parallel-to-serial and serial-to-parallel conversion in a single chip.

The PSI programmable PHY already integrates a 2.5Gbit/s transmit clock-generation PLL, a clock- and data-recovery PLL, and a serialiser/deserialiser (SERDES).

An HSTL I/O parallel bus interface and superior jitter performance ensure robust system operation.

Users can implement additional features in the devices by using the remaining 50,000 logic gates and the 240Kbyte of built-in memory.

The InfiniPHY IP core will be available in July under NDA.

Deliverables for the core will include the datasheet, test benches, documentation, control files and application notes.

The netlist can be downloaded at no cost from the Cypress website.

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