QuadPort DSEs aid datapath management

Cypress Semiconductor has begun sampling the 16K x 18bit and 32K x 18bit versions of its innovative QuadPort Datapath Switch Element (DSE) family.

Cypress Semiconductor has begun sampling the 16K x 18bit and 32K x 18bit versions of its innovative QuadPort Datapath Switch Element (DSE) family.

These devices join the higher capacity QuadPort DSE (configured as 64K x 18bit) - currently in volume production - to offer customers a wider range of storage capacity offerings for data path management.

This high-performance family of communications devices targets high-end storage area networks (SANs), high-speed wide-area networks (WANs) and wireless infrastructure (WIN) applications.

"The QuadPort Datapath Switch Element has changed the way many communications customers design their datapath", said Christopher Norris, Cypress's data communications division vice president.

"By offering three different options, customers will be able to chose the device that fits their specific needs in terms of storage capacity and price".

When considered early in the design cycle, the QuadPort DSE family shows its strength as a communications datapath manager because its combination of logic and memory creates a nonblocking switch architecture.

For example, the devices may be used as: a 4 x 4 switch fabric among four FPGAs, CPLDs, ASICs, PHYs or a series of DSPs; as a redundant datapath generator that allows users to input a single stream of data into one port and then output identical data streams at variable data rates on each of the other ports for fault tolerance; as a packet header manipulation engine, by using two ports to read and write an entire packet and one or two ports to monitor and/or change the header; or as a replacement for the datapath FPGAs, thus lowering the logic gate count for control functions.

"By inserting the QuadPort DSE directly in the datapath next to a backplane physical layer device such as the Cypress HOTLink family, the QuadPort DSE can eliminate the need for using logic in the datapath", said Geoff Charubin, marketing director for Cypress's data communications division.

"Because two ports can handle the dataflow from the physical layer device to the rest of the system, the remaining two free ports can be connected to a processor or programmable logic device to control and manipulate the data.

By refocusing the programmable logic's function from data path to pure control, the system designer can lower the gate count of the programmable logic device as well as the I/O requirements.

This enables designers to use the more efficient CPLD architecture, exemplified by the Cypress Delta39K, instead of cumbersome and costly high-gate-count FPGAs".

All the devices in the QuadPort DSE family offer four completely independent ports that can simultaneously access the data storage array and operate at different frequency domains.

Each port can read or write data at 133MHz, giving the device up to 9.6Gbit/s of data throughput or bandwidth.

Offered in a 272-ball BGA package, measuring 27 x 27mm with a 1.27mm pitch, these devices also come equipped with a built-in self-test and JTAG boundary scan for a high degree of manufacturability.

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