Product category:
Programmable Logic Devices
News Release from: Cypress Semiconductor | Subject: Delta39K200
Edited by the Electronicstalk Editorial
Team on 06 September 2001
Largest CPLD doubles in size
Cypress Semiconductor has announced the availability of the world's largest CPLD, the Delta39K200, which includes 200,000 gates with 3072 macrocells and 480Kbit of embedded memory.
Cypress Semiconductor has announced the availability of the world's largest CPLD, the Delta39K200, which includes 200,000 gates with 3072 macrocells and 480Kbit of embedded communications memory The Delta39K200 CPLD provides double the logic capacity and memory of the previous largest CPLD in the world, the Delta39K100, also from Cypress
This article was originally published on Electronicstalk on 7 Feb 2001 at 8.00am (UK)
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The Delta39K family - which spans seven device densities, ranging from 30,000 to 350,000 gates - is the first CPLD to embed high-performance communications memory and offers more memory than any FPGA.
The Delta39K architecture consists of logic block clusters (LBCs), each of which has 128 macrocells - eight 16-cell macrocell logic blocks - connected by a Programmable Interconnect Matrix (PIM).
Each LBC has 16Kbit of single-port SRAM cluster memory, configurable as synchronous or asynchronous and as x1, x2, x4 or x8.
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The cluster memory can be cascaded with other cluster memory blocks to implement wider and deeper memory functions.
In addition to cluster memory blocks, each LBC has an associated channel memory block.
The 4Kbit channel memory uses Cypress's true-dual-ported cell to offer optimised dual-port and FIFO memory with completely independent write and read clocks.
Each channel memory block includes FIFO control and the dual-port arbitration logic needed to implement extremely fast and powerful specialty memory functions.
The Delta39K device offers FIFO performance as high as 200MHz.
The channel memory, like the cluster memory, is configurable as x1, x2, x4 or x8 and its width and depth can be expanded.
The LBCs and channel blocks communicate through abundant vertical and horizontal routing channels.
These channels also connect to a block of I/O pins at each end to provide maximum pinout flexibility and true in-system reprogrammability.
This gives designers the flexibility to change a design with the confidence that speed and pinout will not be altered.
Delta39K CPLDs are offered with a pin-to-pin propagation delay as low as 7ns and true in-system performance in excess of 233MHz.
The devices are manufactured using a 0.18-micron six-layer metal process, the most aggressive process ever used for a CPLD.
Innovative package options include an embedded nonvolatile Flash memory die with the Delta39K die, creating a unique nonvolatile solution and eliminating the need for an external boot PROM.
Each device in the Delta39K family includes a programmable, Spread Aware phase locked loop - with unmatched multiply, divide and clock edge control options - that provides four global clocks to all logic clusters, memories and I/O cells to maintain precise on- and off-chip timing.
The Delta39K family of CPLDs are fully supported by Cypress's Warp Release 6.1 design tool suite.
Warp is a fully integrated programmable logic design environment that accepts VHDL, Verilog, finite state machine and schematic entry as design input mechanisms.
Warp also performs synthesis and fitting in a single step to speed the design process.
In addition, Warp features an Architecture Explorer and static timing analyser to quickly pinpoint design fitting and critical path timing to aid in fast debugging and timing closure of logic designs.
Warp also includes a fully capable simulation tool for design verification.
The 200,000-gate Delta39K200 devices are sampling now and production volumes will be available soon.
Volume pricing in 2001 for the Delta39K200 starts at $65.00.
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