Cores for high-speed network infrastructure

Edited by the Electronicstalk editorial team Oct 16, 2001

Cypress Semiconductor and MorethanIP are to make MorethanIP's IP cores available for the Cypress PSI family of programmable physical layer devices and the Delta39 family of CPLDs.

Cypress Semiconductor and MorethanIP are to make MorethanIP's IP cores available for the Cypress Programmable Serial Interface (PSI) family of programmable physical layer (PHY) devices and the Delta39K family of complex programmable logic devices (CPLDs).

The inclusion of MorethanIP in the IP Oasis partnership programme reinforces Cypress's strategy of providing leading-edge solutions for its data communications customers.

The IP cores simplify IP integration into broadband optical, SONET/SDH system designs, providing flexibility and shortening design cycle time.

The IP cores will be available as netlists or RTL source code and will be optimised and prefit for both the PSI and Delta39K device families.

"The IP/cores from MorethanIP enable Cypress to provide comprehensive communications interface solutions for the rapidly-growing OC-48/STM-16 and OC-192/STM-64 data communications markets as designers combine PSI PHYs or Delta39K CPLDs with our framers, network search engines, network coprocessors and datapath switching elements", said Chris Norris, Vice President of Cypress's Data Communications Division.

"MorethanIP's IP/cores complement Cypress's programmable platforms", said Deepak Sharma, senior IP and EDA marketing manager of Cypress's Data Communications Division.

"The programmability allows integration of custom IP with the POS-PHY L3/Flexbus-4 IP/cores to enable standard communications interfaces to processors, framers and other chips on the board".

"Partnering with Cypress allows us to offer hardware-verified system solutions to designers through leading-edge products such as the PSI and Delta39K families", said Francois Balay, MorethanIP's director of business development.

"This is an opportunity for us to highlight our extensive experience in hardware and software development of high-speed solutions for data and telecommunications applications".

The Flexbus 4 IP core enables packet-over-SONET/SDH (POS) networking routers to send native IP packets directly over SONET/SDH frames.

It enables the transfer of data between a physical-layer framer chip and a link layer processor at 10Gbit/s.

It is compliant with Optical Internetworking Forum specification OIF-SPI4-01.0.

Both Flexbus 4 and SPI-4 Phase 1 transfer 64bit per clock cycle with out-of-band addressing.

Flexbus 4 has an optional 16-bit path for OC-48/STM-16 applications.

The POS-PHY Level 3 (PL3) interface defines operations between PHYs (such as ATM, POS and Gigabit Ethernet framers) and link layer devices (such as ATM, Internet Protocol and Gigabit Ethernet forwarding devices) at the OC-48/STM-16 aggregate line rate.

The PL3 interface is used in IP routers, switches, link layer interfaces to processors, and traffic management devices.

The MorethanIP PL3 IP core is compliant with the POS-PHY L3 of the Saturn Development Group, ATM Forum specification AF-PHY-0143.000 and Optical Internetworking Forum specification OIF2000.008.3.

The IP cores are available as netlists optimised for use with Cypress's Warp development environment.