Big wide dual-port RAM runs simultaneously

Now in full production, Cypress Semiconductor reckons that at 9Mbit its CY7C0853V is the world's highest density true dual-port memory.

Now in full production, Cypress Semiconductor reckons that at 9Mbit, its CY7C0853V is the world's highest density true dual-port memory.

The CY7C0853V is the latest addition to Cypress's broad portfolio of high-density dual-ports including the 4, 2 and 1Mbit devices currently in production.

Cypress's true dual-port memories are specifically designed to address the memory buffering requirements of high-performance wireless basestations, storage networks and wide-area networks.

The CY7C0853V provides 9Mbit of synchronous, pipelined dual-ported memory capable of buffering large packets of data between two independent clock domains.

Configured as a 256K x 36bit device, it provides up to 9.6Gbit/s of bandwidth and allows for easy interface to wide buses.

Unlike alternative bank-switchable devices, the CY7C0853V is a true dual-port, providing simultaneous read and write access to any cell in its memory array from either of its two ports.

In addition, the two ports may operate at independent clock speeds, allowing complete decoupling of the devices being interfaced.

The devices are available in a 172-pin BGA package at up to 133MHz.

The 4, 2, and 1Mbit devices are offered in the 172 BGA package, as well as TQFPs.

"High density is critically important to support the buffering and internal queuing required by communications systems as line rates and processing speeds increase.

The density and bandwidth provided by Cypress's newest dual-ports is ideally suited to wireless basestations and storage networks", said Christopher Norris, Vice President of Cypress's Data Communications Division.

"By introducing the world's first 9Mbit true dual-port solution Cypress maintains its technology leadership position in specialty memories for the communications market".

In many wireless infrastructure applications, multi-port memories are used to both store and manipulate packet data between baseband processing and digital signal processing system devices operating in different clock domains.

Wide area and storage networks employing high-performance communications protocols (such as OC-48, Gigabit Ethernet, or Fibre Channel) also use high-density multiported memories to buffer data packets between the backplane interconnect and the data port to avoid loss of data and maintain efficient flow control.

The size of the buffer is typically driven by the difference between the input and output clocking speeds, the buffering time required by the system, and the bus width.

These requirements dictate the need for a high density multi-port memory in communication systems as system speeds continue to increase.

The multiport memory may also be used in conjunction with a high density CPLD (such as Cypress's Delta39K family) which controls the data flow and partitioning of the memory.

The partitioning can be done to create multiple sections or "queues" inside of the memory to alleviate common networking issues such as head of line blocking and enable quality of service classification.

The high density of the Cypress 9Mbit dual-port will allow system designers the most queue density capability of any true dual-port memory, while the high speed will allow them to maximise the bandwidth of their system.

The 9Mbit dual-port is the latest in a line of Cypress innovations in specialty memories to address the data buffering and interprocessor communication needs of high performance communications systems.

In addition, Cypress is in full production of its 4Mbit dual port family in x36 configurations at up to 150MHz.

Production quantities of all densities are available now.

The 9Mbit devices will be priced as low as $98 in quantities of 10k units.

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