Product category:
Memory Devices and Modules
News Release from: Cypress Semiconductor | Subject: QuadPort DSE family
Edited by the Electronicstalk Editorial
Team on 03 October 2002
Switch allows four-way simultaneous
memory access
A new high-performance QuadPort DSE datapath switching element supports bandwidths up to 27Gbit/s and provides densities up to 5Mbit.
A new high-performance QuadPort DSE datapath switching element supports bandwidths up to 27Gbit/s and provides densities up to 5Mbit Cypress's QuadPort DSE is a four-port switching element that allows simultaneous access to an integrated memory array from each of its completely independent ports which can operate in different frequency domains
This article was originally published on Electronicstalk on 9 Jul 2008 at 8.00am (UK)
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Cypress pioneered the concept of QuadPort DSEs with the introduction of its 1Mbit family (10Gbit/s bandwidth) in 2001, including functions such as 2 x 2 switching, datapath aggregation, redundant data generation and packet header manipulation.
This next-generation QuadPort DSE family adds higher bandwidth (four ports x 167MHz x 40bit) and higher storage capacity (up to 5Mbit).
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At these unprecedented levels of performance and storage, Cypress doubles the bandwidth and over quadruples the density of any competitive offerings.
"These high-performance devices put Cypress a generation ahead of the competition and allow our customers to create innovative system architectures, thereby achieving higher performance and efficiency", said Geoff Charubin, Marketing Director for Cypress's Data Communications Division.
"By providing up to 5Mbit of integrated memory at 27Gbit/s operation, the QuadPort DSE enables our customers to reduce the need for multiple devices, thereby significantly improving their cost-per-megabit of capacity and cost-per-gigabit of bandwidth".
The QuadPort DSE shows its strength as a communications datapath enabler because its combination of logic and memory creates a nonblocking switch architecture.
Maximum system benefit is gained by planning for usage during the architectural stage of design.
For example, the devices may be used as: a 2 x 2 switch fabric among four devices such as FPGAs, CPLDs, ASICs, PHYs or a series of DSPs; a datapath aggregator that allows multiplexing multiple low-bandwidth data streams into a single high-bandwidth data stream; a redundant datapath generator that allows users to input a single stream of data into one port and then output identical data streams at variable data rates on each of the other ports for fault tolerance and parallel processing; or as a packet-header manipulation engine that uses two ports to read and write an entire packet and one or two ports to monitor and/or change the header, which provides an alternative for high-cost data-path FPGAs by lowering its logic-gate count, I/O number, and internal memory requirements.
When used in conjunction with the Cypress OC-48 port serdes, Delta39K CPLDs and Hotlink family of backplane physical-layer devices, the QuadPort DSE family provides a complete system solution for customers building communications linecards.
Communications systems customers who are already familiar with Cypress's quad-datarate RAM, Beast FIFO, synchronous SRAM, CPLD, and clock solutions will also benefit from the QuadPort DSE family.
This QuadPort DSE family of devices offers configurable I/Os supporting LVTTL and SSTL2 standards, enabling seamless interface with PLDs, FPGAs, ASICs, next-generation DSPs, control processors and other memory devices on the board.
These devices also come with advanced features such as impedance matching on data outputs to reduce transmission line effects; burst counters for enabling block transfer of data; and memory block retransmit for rereading a block of data in case of transmission failure.
All QuadPort DSEs offer four completely independent ports that can simultaneously access the data storage array and operate in different frequency domains.
Each port can read or write data up to 167MHz, giving the device up to 27Gbit/s of data throughput or bandwidth.
Offered in a 676-ball PBGA package measuring 27 x 27mm with a 1.0mm pitch, these devices are compliant with IEEE1149.1 JTAG boundary scan for a high degree of manufacturability.
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