Product category:
Memory Devices and Modules
News Release from: Cypress Semiconductor | Subject: CY7C15XXV18 family
Edited by the Electronicstalk Editorial
Team on 24 March 2004
Quad-datarate SRAMs reach 72Mbit
Cypress Semiconductor has begun sampling a new family of 72Mbit QDR-II and DDR-II devices, the world's highest density and highest bandwidth SRAMs.
Cypress Semiconductor has begun sampling a new family of 72Mbit QDR-II (quad datarate) and DDR-II (double datarate) devices, the world's highest density and highest bandwidth SRAMs Cypress's new memory chips deliver up to 50% more system level bandwidth and accelerate read/write capabilities in a variety of data intensive applications, including switches, routers, servers, storage appliances, wireless basestations and test equipment
This article was originally published on Electronicstalk on 9 Jul 2008 at 8.00am (UK)
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"Until now, manufacturers could not get QDR SRAMs larger than 36Mbit, and the burst-of-two (B2) architecture has been limited to 200MHz", said Tony Alvarez, Vice President of Cypress's Memory Products Division.
"Cypress's 72Mbit QDR devices will shatter these performance milestones, giving manufacturers the density and robust performance they need to expand network capabilities and offer more services.
The devices will operate at clock speeds up to 250MHz and provide up to 36Gbit/s of bandwidth".
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"For the second time in recent months, Cypress has leapfrogged the competition at 72Mbit", said Betsy Van Hees, Senior Analyst at iSuppli Corp, referring to the company's 72Mbit synchronous SRAM samples, announced last July.
"The timing couldn't be better, with datacomms and networking sectors showing new signs of growth".
"This announcement", Van Hees continued, "should help Cypress build upon its strong position in SRAMs, where it is currently one of the world's top suppliers, with approximately 14% market share".
Cypress new CY7C15XXV18 family of SRAMs supports the LA-1 bus interface, used by a wide array of network processors, including Intel's IXP family and the DDR-II SRAM interface used by such network processors as Agere Systems' PayloadPlus.
The devices increase bandwidth by supporting separate data inputs and outputs for simultaneous read and write operations.
Their low initial latency - 1.5 cycles for QDR-II and one cycle for QDR - maximises the efficiency of algorithmic lookup tables, statistics tracking and data buffering.
In addition to superior performance, Cypress's 72Mbit devices also offer several key form factor characteristics, including a 165 fBGA package, which is 40% smaller than alternative solutions.
The devices are also pin-compatible with products from other QDR Co-Development Team members, including IDT, NEC, Renesas and Samsung, and those from former member Micron, which are now being offered by Cypress.
They are manufactured using Cypress's industry leading 90nm process technology.
Cypress's CY7C15XXV18 family will be sampling five core configurations by the middle of this year, with production starting in late 2004.
The CY7C1512V18, sampling today at 200MHz, is a QDR-II B2 device configured as 4M x 18bit.
A 250MHz version of the part will be available by mid-year.
Another 250MHz QDR-II B2 device, the CY7C1525V18, is configured as 8M x 9bit and will begin sampling by Q3.
Three additional devices will begin sampling in the second and third quarters, including: the CY7C1515V18, a QDR-II B4 device configured as 2M x 36bit; the CY7C1518V18, a 4M x 18bit DDR-II B2 device; and the CY7C1523V18, a DDR-II SIO device configured as 4M x 18bit.
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