Product category:
Design and Development Software
News Release from: Denali Software | Subject: Blueprint
Edited by the Electronicstalk Editorial
Team on 08 August 2005
Software takes on SoC register
management
New software boosts SoC design efficiency by automating the generation and management of the vast numbers of on-chip control registers in complex chip designs.
Denali Software describes Blueprint as the latest advancement in electronic system level (ESL) design Blueprint automates the generation and management of the hundreds, and often thousands, of control registers used in complex chip designs as a source for efficiency improvements in system-on-chip (SoC) design
This article was originally published on Electronicstalk on 5 Aug 2005 at 8.00am (UK)
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Created for chip developers, Blueprint addresses all elements of register management, including description and generation of control register logic, assertions and verification models, firmware interfaces and the accurate documentation necessary for system-level design.
The vast numbers of on-chip registers that are part of all complex designs define the software interface to the chip, and usually represent the largest portion of the chip specification or programmers guide.
Blueprint eliminates tedious and error-prone processes of manually managing registers, and enables design, verification and firmware teams to work more efficiently from consistent and synchronised views of the chip design.
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"There is a great deal of value in having a tool to generate the hundreds or thousands of registers in today's ASIC designs", says Michael Uhler, Chief Technology Officer (CTO) at MIPS Technologies.
"More importantly, Denali's Blueprint product gives system designers the ability to automatically synchronise and generate all the different views for these registers".
"Having accurate documentation, assertions, field maps, and header file information has a huge effect on both hardware and software developers - it can ultimately make or break a chip's development schedule".
"As a leading provider of SoC design and verification solutions, Mentor Graphics is committed to delivering high-quality products that provide real value to our customers", adds Serge Leef, General Manager of the SoC Verification Division at Mentor Graphics.
"A key part of this value lies in enabling integration with other best-in-class products".
"For several years, our Seamless and Platform Express customers have enjoyed a very complementary relationship with Denali's products, and we see that same synergy with Blueprint, especially for IP-based design".
"Blueprint automates the generation of accurate, consistent specifications and integration views that are key for rapid integration of IP.
This type of product can provide significant value for both IP providers and IP consumers".
"It is critical for this industry to deliver significant productivity gains across all aspects of chip design, including design, verification and software development", remarks Denali CTO Mark Gogolewski.
"Blueprint represents a pragmatic approach to ESL, offering immediate gains in productivity and quality without requiring a methodology overhaul".
Denali Blueprint is a third-generation software product, and has been used successfully in numerous large SoC designs.
Denali acquired the technology licence for commercial product deployment.
Blueprint is an ESL tool in use by design, verification, software and firmware engineers to automate the creation and management of control registers and all associated models, design views and documentation.
From a register description language (RDL) input, Blueprint generates various outputs for hardware design, software development, verification and documentation.
For design, Blueprint produces synthesisable Verilog, SystemVerilog or VHDL code for control registers and also generates Open Verification Library (OVL) assertions that ensure the correct operation of the register and generated logic.
For functional verification, Blueprint outputs models of the registers for use in C/C++, SystemC, OpenVera, e, Verilog and SystemVerilog.
For software, Blueprint generates headers, classes with access methods and a complete Hardware Abstraction Layer (HAL) to enable software developers to be productive as soon as the architecture is defined and isolate them from low-level design changes.
Additionally, Blueprint generates test cases for pre- and post-silicon validation of the generated logic.
For documentation, Blueprint outputs files compatible with user templates for Framemaker, MS-Word, HTML, XML or SGML based documentation.
The Blueprint architecture is extensible because of a well-defined object-oriented architecture, enabling design teams to customise and create new code generators for their particular applications.
Blueprint is available now and is priced at $500,000 per year for an enterprise site licence.
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