Product category:
Design and Development Software
News Release from: Denali Software | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial
Team on 30 June 2006
Memory controller IP supports encounter
synthesis
Cadence Design Systems has announced support for Cadence Encounter RTL Compiler global synthesis on Databahn memory controller products.
Cadence Design Systems has announced support for Cadence Encounter RTL Compiler global synthesis on Databahn memory controller products Encounter RTL Compiler synthesis enables Denali customers to achieve smaller, faster and lower power implementations for Databahn DRAM controller designs
This article was originally published on Electronicstalk on 5 Aug 2005 at 8.00am (UK)
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DDR memory systems have emerged as a critical design requirement for enabling high performance in virtually all electronics products, including everything from cell phones to set top boxes.
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DRAM memory systems require specialized tuning and tailoring to achieve specific performance requirements for each unique design or application.
The Databahn memory controller uses simple synthesis script modifications combined with Encounter RTL Compiler multi-objective optimization to achieve significant advantages in area, speed and performance.
"Systems today demand high performance DDR memory controllers, and designers implementing these controllers require state-of-the-art synthesis tools".
"We are excited to enable our customers with synthesis solutions from Cadence," said Brian Gardner, vice president of IP products at Denali.
"What impressed us most about Encounter RTL Compiler global synthesis is that it was easy to set up and use, and it worked perfectly out of the box".
"Databahn customers using Encounter now have access to an optimal synthesis solution that provides excellent power-vs.-area tradeoffs for SoC design." Encounter RTL Compiler global synthesis, a key technology of the Cadence Encounter digital IC design platform, improves performance, reduces die sizes, lowers power consumption, and speeds up design closure through place and route.
Cadence defines this metric as quality of silicon (QoS).
This ability to produce smaller, faster and cooler chips in less time has increased customer competitiveness and reduced overall costs.
"Denali is the leading design and verification solution provider for standard interfaces and we are extremely happy that Encounter RTL Compiler has helped to optimise customer implementations of Denali's Databahn memory controller cores," said Dr Chi-Ping Hsu, corporate vice president at Cadence.
"This is yet another example of Cadence's successful IP strategy with an important IP partner".
"Encounter RTL Compiler synthesis is employed by companies worldwide to create smaller, faster, lower power, and higher quality designs to address the challenges of today's competitive markets.".
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