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News Release from: Denali Software | Subject: DDR2 SDRAM PHY
Edited by the Electronicstalk Editorial
Team on 24 September 2007
Memory PHY reduces LSI design risks
DDR2 SDRAM PHY design can be prototyped on the Xilinx Virtex-5 FPGA before progressing to Tokyo Electron Device ASICs.
Tokyo Electron Device and Denali Software have collaborated to develop and release a DDR2 SDRAM PHY design that runs on the Xilinx Virtex-5, the largest and fastest FPGA in the world The PHY is fully compatible with DDR PHY Interface (DFI), which is the industry-standard interface for DDR memory controller and PHY
This article was originally published on Electronicstalk on 5 Aug 2005 at 8.00am (UK)
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The DDR PHY Interface (DFI) specification, developed by ARM, Denali, Intel, Rambus, Samsung, and Synopsys, defines a common interface between the DDR memory controller logic and the DDR PHY interface in order to reduce cost and time to market for DDR DRAM memory system development.
Tokyo Electron Device ASIC customers now have access to DDR PHY designs, in 90nm process technologies and below, that integrate seamlessly with other DFI compatible designs, including Denali's Databahn DDR memory controller products.
"We are delighted we could develop DFI DDR2 SDRAM PHY Design for Virtex-5, which is Xilinx's state-of-the-art FPGA, with the support of Denali Software", says Masami Hasegawa, Director and Xilinx Product Manager of Tokyo Electron Device.
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"We expect this release will accelerate the promotion of Virtex-5 as well as our evaluation platform and design services in the worldwide".
"The DFI certified DDR2 SDRAM PHY design allows designers to develop large-scale integration (LSI) faster and with less risk", says Tadashi Arai, Director of Marketing Department, Xilinx Japan.
"We feel that Xilinx Virtex-5 FPGA and this PHY design provides designers with a more effective way for both ASIC prototyping and mass-production with DDR2 controller design".
The release of the DDR2 SDRAM PHY will help designers to develop LSIs faster with less risk using a high-speed DDR2 interface, relieving developers of time-consuming development and integration tasks needed for special design of the DDR memory controller.
Combining DDR2 SDRAM PHY and Denali's Databahn memory controller design IP, featuring technology proven in LSI implementation and Tokyo Electron Device's "inrevium" brand Virtex-5 Multi-Application Evaluation Platform (TB-5V-LX110/220/330-DDR2), developers can effectively improve the time to market cycle.
"As DDR DRAMs achieve speeds up to 1600Mbit/s, high-performance DDR interfaces become a critical factor in overall system performance", says Kenichi Sakamaki, General Manager of Denali Software Japan.
"Designers, faced with challenges in achieving timing closure, need a complete, integrated solution consisting of digital DDR memory controllers and a DDR PHY that are proven and meet design requirements".
"The DFI specification provides a clean boundary between these two memory system components, and enables developers to use our high-quality, silicon-proven DDR IP solution for a broad set of process technologies".
"Tokyo Electron Device's new DFI compatible DDR PHY designs are leading edge solutions for ASIC development, and provide customers with a meaningful advantage in DDR memory system development".
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